Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-22
2008-07-22
Torres, Joseph D. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S728000, C714S729000
Reexamination Certificate
active
07404127
ABSTRACT:
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.
REFERENCES:
patent: 5701308 (1997-12-01), Attaway et al.
patent: 6343365 (2002-01-01), Matsuzawa et al.
Bassuk Lawrence J.
Brady W. James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Torres Joseph D.
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