Stress liner for integrated circuits

Details Stress liner for integrated circuits Stress liner for integrated circuits

2008-06-10

2008-06-10

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S680000, C438S692000, C257SE21170, C257SE21304, C257SE21229, C257SE21231, C257SE21293, C257SE21632

Reexamination Certificate

active

07384833

ABSTRACT:
In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

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H.S. Yang, et al., “Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing,” IEDM Tech. Dig., pp. 1075-1078, Dec. 2004.
PCT International Search Report for PCT/US07/03352 mailed Sep. 24, 2007; total of 2 sheets.

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