Transparent burst access to data having a portion residing in ca

Details Transparent burst access to data having a portion residing in ca Transparent burst access to data having a portion residing in ca

1996-06-14

1998-09-01

Sheikh, Ayaz R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711100, G06K 1300

Patent

active

058023232

ABSTRACT:
A bus control interface selectively and transparently couples a bus agent to a cache and to a memory to provide transparent burst access to addressable data having a portion residing in cache and a portion residing in memory. The bus control interface steers transactions to the cache or to the memory depending on where the data resides. In this way, the bus control interface supports, without a disconnect, burst read transactions that cross cache line boundaries. The bus control interface also supports bus watching single-word read (and write) transactions as well as burst write transactions.

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