Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-06-03
2008-06-03
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S301000, C438S592000, C257SE27108
Reexamination Certificate
active
07381602
ABSTRACT:
A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined tensile intrinsic stress of about 900 MPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, tensile stress is created in the channel region. The tensile stress leads to an increase of the electron mobility in the channel region.
REFERENCES:
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 2004/0029323 (2004-02-01), Shimizu et al.
patent: 2005/0247926 (2005-11-01), Sun et al.
patent: 2006/0009041 (2006-01-01), Iyer et al.
Frohberg Kai
Hohage Joerg
Ruelke Hartmut
Advanced Micro Devices , Inc.
Nguyen Thanh
Williams Morgan & Amerson P.C.
LandOfFree
Method of forming a field effect transistor comprising a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a field effect transistor comprising a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a field effect transistor comprising a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2805507