Strained Si/SiGe/SOI islands and processes of making same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S295000, C438S404000

Reexamination Certificate

active

07368790

ABSTRACT:
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use of a minifield oxidation process. The recess is filled to form a shallow trench isolation structure. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

REFERENCES:
patent: 5461243 (1995-10-01), Ek et al.
patent: 5759898 (1998-06-01), Ek et al.
patent: 5949102 (1999-09-01), Saida et al.
patent: 6110793 (2000-08-01), Lee et al.
patent: 6204145 (2001-03-01), Noble
patent: 6274457 (2001-08-01), Sakai et al.
patent: 6476434 (2002-11-01), Noble et al.
patent: 6583052 (2003-06-01), Shin
patent: 6649480 (2003-11-01), Fitzgerald et al.
patent: 6703648 (2004-03-01), Xiang et al.
patent: 6855649 (2005-02-01), Christiansen et al.
patent: 6900094 (2005-05-01), Hammond et al.
patent: 6963078 (2005-11-01), Chu
patent: 7153753 (2006-12-01), Forbes
patent: 7198974 (2007-04-01), Forbes
patent: 7202530 (2007-04-01), Forbes
patent: 7273788 (2007-09-01), Forbes
patent: 2002/0001965 (2002-01-01), Forbes
patent: 2002/0135020 (2002-09-01), Skotnicki et al.
patent: 2002/0163045 (2002-11-01), Farrar
patent: 2003/0013323 (2003-01-01), Hammond et al.
patent: 2003/0027406 (2003-02-01), Malone
patent: 2003/0218189 (2003-11-01), Christiansen et al.
patent: 2004/0048450 (2004-03-01), Tewwt et al.
patent: 2006/0011982 (2006-01-01), Forbes
Belford, Rona E., et al., “Performance-Augmented CMOS Using Back-End Uniaxial Strain”,IEEE 60th DRC, Conference Digest Device Research Conference, 2002, (Jun. 24-26, 2002),41-42.
Biever, Celeste, “Secret of ‘strained silicon’ revealed: behind closed doors, Intel has perfected a novel way to improve chip performance.”,New Scientist, 180(i2426-2428), (Dec. 20, 2003),27.
Clifton, P A., et al., “A process for strained silicon n-channel HMOSFETs”,ESSDERC'96, Proceedings of the 26th European Solid State Device Research Conference, (Sep. 1996),519-22.
Fischetti, M V., et al., “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys”,Journal of Applied Physics, 80(4), (Aug. 15, 1996),2234-2252.
Forbes, K Y., “Non-Volatile Memory Device with Tensile Strained Silicon Layer”, U.S. Appl. No. 11/260,339 (client ref No. 05-0753—Leffert file), 26 pgs.
Ghani, T., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”,Technical Digest IEEE International Electron Devices Meeting, (Dec. 2003),978-980.
Jurczak, M, “SON (silicon on nothing)-a new device architecture for the ULSI era”,VLSI Technology, 1999,Digest of Technical Papers. 1999 Symposium on, Jun. 14-16, 1999,29-30.
Kal, S., et al., “Strained Silicon-SiGe Devices Using Germanium Implantation”,IETE Journal of Research, 43(2-3), (Mar. 1997),185-192.
Lu, X., et al., “SiGe and SiGeC Surface Alloy Formation Using High-Dose Implantation and Solid Phase Epitaxy”,Proceedings of the 11th International Conference on Ion Implantation Technology, Austin, TX,(1997),686-689.
Meyerson, B S., “SiGe-Channel Heterojunction p-MOSFET's”,IEEE Transactions on Electron Devices, 41(1), Authors: Verdonckt-Vandebroek, S.; Crabbe, E.F.; Meyerson, B.S.; Harame, D.L.; Restle, P.J.; Stork, J.M.C.; Johnson, J.B,(Jan. 1994),90-101.
Mizuno, T, et al., “Advanced SOI-MOSFETs with Strained-Si Channel for High Speed CMOS Electron/Hole Mobility Enhancement”,2000 Symposium on VLSI Technology. Digest of Technical Papers, (2000),210-211.
Moran, Peter, “Strain Relaxation in Wafer-Bonded SiGe/Si Heterostructures Due to Viscous Flow of an Underlying Borosilicate Glass”,Electronic Materials Conference, Santa Barbara, Jun. 2002, Abstract,pp. 8-9.
Nayak, D. K., “High performance GeSi quantum-well PMOS on SIMOX”,International Electron Devices Meeting 1992. Technical Digest, (1992),777-780.
Omi, Hiroo, et al., “Semiconductor Surface with Strain Control”, http://www.brl.ntt.co.jp/J/kouhou/katsudou/report00/E/report04—e.html.
Paine, D. C., et al., “The Growth of Strained Si]-xGex Alloys on (100) Silicon Using Solid Phase Epitaxy”,Journal of Materials Research,5(5), (May 1990),1023-1031.
Rim, Kern, et al., “Fabrication and analysis of deep submicron strained-Si n-MOSFET's”,IEEE Transactions on Electron Devices, 47(7), (Jul. 2000),1406-1415.
Rim, Kern, et al., “Strained Si NMOSFETs for High Performance CMOS Technology”,2001 Symposium on VLSI Technology. Digest of Technical Papers, (2001),59-60.
Rim, Kern, et al., “Transconductance enhancement in deep submicron strained Si n-MOSFETs”,International Electron Devices Meeting 1998. Technical Digest, (1998),707-710.
Sugiyama, N, et al., “Formation of strained-silicon layer on thin relaxed-SiGe/SiO/sub 2//Si structure using SIMOX technology”,Thin Solid Films,369(1-2), (Jul. 2000),199-202.
Takagi, Shin-ichi, “Strained-Si- and SiGe-On-Insulator (Strained-SOI and SGOI) MOSFETs for High Performance/Low Power CMOS Application”,IEEE Device Research Conference, 2002. 60th DRC. Conference Digest, (2002),37-40.
Xiao, Q., et al., “Preparation of thin Strained Si Film by Low Temperature Ge Ion Implantation and High Temperature Annealing”,Solid-State and Integrated Circuits Technology, 2004. Proceedings 7th Int'l Conf., 3(3), (Oct. 18, 2004),2163-2166.
Yin, Haizhou, “High Ge-Content Relaxed Sil-xGex Layers by Relaxation on Complaint Substrate with Controlled Oxidation”,Electronic Materials Conference, Santa Barbara, Jun. 2002, 8.
“U.S. Appl. No. 10-210373 final office action mailed Jun. 11, 2007”, 17 PGS.
“U.S. Appl. No. 10-210373 non-final office action mailed Jan. 24, 2007”, 17 PGS.
“U.S. Appl. No. 10-379749 Amendment under 37 C.F.R. filed Nov. 1, 2006”, 3 PGS.
“U.S. Appl. No. 10-379749 Notice of allowance mailed Dec. 13, 2004”, 6 PGS.
“U.S. Appl. No. 10-379749 Notice of allowance mailed Aug. 3, 2006”, 2 PGS.
“U.S. Appl. No. 10-425484 non-final office action mailed Jun. 28, 2004”, 5 PGS.
“U.S. Appl. No. 10-425484 Notice of allowance mailed Dec. 20, 2004”, 2 PGS.
“U.S. Appl. No. 10-425484 Notice of allowance mailed Dec. 21, 2006”, 4 PGS.
“U.S. Appl. No. 10-425484 Response filed Sep. 28, 2004 to non-final office action mailed Jun. 28, 2004”, 19 PGS.
“U.S. Appl. No. 10-425797 non-final office action mailed Nov. 17, 2004”, 15 PGS.
“U.S. Appl. No. 10-425797 non-final office action mailed Apr. 26, 2004”, 16 PGS.
“U.S. Appl. No. 10-425797 non-final office action mailed May 19, 2005”, 10 PGS.
“U.S. Appl. No. 10-425797 Notice of allowance mailed Nov. 4, 2005”, 4 PGS.
“U.S. Appl. No. 10-425797 Response filed Feb. 17, 2005 to non-final office action mailed Nov. 17, 2004”, 21 PGS.
“U.S. Appl. No. 10-425797 Response filed Aug. 26, 2004 to non-final office action mailed Apr. 26, 2004”, 21 PGS.
“U.S. Appl. No. 10-425797 Response filed Aug. 4, 2005 to non-final office action mailed May 19, 2005”, 17 PGS.
“U.S. Appl. No. 10-431134 Amendment under 37 C.F.R. filed Sep. 28, 2005”, 16 PGS.
“U.S. Appl. No. 10-431134 non-final office action mailed Dec. 23, 2004”, 5 PGS.
“U.S. Appl. No. 10-431134 Notice of allowance mailed Jun. 28, 2005”, 4 PGS.
“U.S. Appl. No. 10-431134 response filed Mar. 23, 2005 to non-final office action mailed Dec. 23, 2004”, 19 PGS.
“U.S. Appl. No. 10-431337 Notice of allowance mailed Jan. 27, 2005”, 4 PGS.
“U.S. Appl. No. 10-431137 Notice

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Strained Si/SiGe/SOI islands and processes of making same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Strained Si/SiGe/SOI islands and processes of making same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Strained Si/SiGe/SOI islands and processes of making same will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2805055

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.