Method of making a multi-bit non-volatile memory (NVM) cell...

Details Method of making a multi-bit non-volatile memory (NVM) cell... Method of making a multi-bit non-volatile memory (NVM) cell...

2008-04-29

2008-04-29

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21179

Reexamination Certificate

active

07364970

ABSTRACT:
A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.

REFERENCES:
patent: 6011725 (2000-01-01), Eitan
patent: 6330184 (2001-12-01), White et al.
patent: 6417049 (2002-07-01), Sung et al.
patent: 6492228 (2002-12-01), Gonzalez et al.
patent: 6706599 (2004-03-01), Sadd et al.

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