Folded bitline dynamic RAM with reduced shared supply voltages

Details Folded bitline dynamic RAM with reduced shared supply voltages Folded bitline dynamic RAM with reduced shared supply voltages

1990-09-19

1992-03-03

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365149, 365208, 365222, G11C 700, G11C 1124

Patent

active

050938088

ABSTRACT:
A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.

REFERENCES:
patent: 4780850 (1988-10-01), Miyamoto et al.

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