Method and apparatus for deferred decision signal quality...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S704000

Reexamination Certificate

active

07363562

ABSTRACT:
A signal analysis circuit includes a sampling circuit operative to sample the characteristics of an input signal at various points within a bit window in response to a sample clock signal. A sampling control circuit is coupled to the sampling circuit and is operative to provide the sample clock signal in response to a sample control signal. The sample clock signal provides a variable time function such that the input signal characteristics may be sampled at several times during the input signal or bit window period. A control circuit is coupled to the sampling circuit and the sampling control circuit, and is operative to provide the sample control signal in response to the number of times the input signal is within a signal characteristic of interest. In an exemplary embodiment, the characteristic of interest is a reference pattern that may be synchronized with the input data signal. The reference pattern is provided a pattern generation circuit that is resident within a larger comparison and counting circuit.

REFERENCES:
patent: 6430720 (2002-08-01), Frey et al.
patent: 6728311 (2004-04-01), Waschura et al.
patent: 2006/0067392 (2006-03-01), Waschura
patent: 1143654 (2001-10-01), None

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