Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-03-08
2011-03-08
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S228000, C438S231000, C438S247000, C438S305000, C438S549000, C257S335000, C257S336000, C257S371000, C257S343000, C257S408000, C257SE21417, C257SE21642, C257SE21644
Reexamination Certificate
active
07902020
ABSTRACT:
A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from the second conductivity-type well.
REFERENCES:
patent: 6902959 (2005-06-01), Kim et al.
patent: 2010/0032758 (2010-02-01), Wang et al.
patent: 10-2006-0022996 (2006-03-01), None
patent: 10-2008-0017634 (2008-02-01), None
Ahmadi Mohsen
Dongbu Hi-Tek Co., Ltd.
Garber Charles D
Sherr & Vaughn, PLLC
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