Latch pulse delay control

Details Latch pulse delay control Latch pulse delay control

2011-03-08

2011-03-08

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S194000

Reexamination Certificate

active

07903475

ABSTRACT:
A novel memory circuit includes a pulse line, a memory latch including an enable port, and a pulse delay element interposed between the pulse line and the enable port of the memory latch. In a particular embodiment, the pulse delay element includes a series of logic gates. In a more particular embodiment, the series of logic gates include a feedback line for disconnecting the enable port from the pulse line. In another particular embodiment, the enable ports of two different memory latches are connected to the same pulse line via two different latch pulse delay elements, each having different delay times. In a more particular embodiment, the data output port of the first latch is connected to the data input port of the second latch.

REFERENCES:
patent: 6078528 (2000-06-01), Johnson et al.

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