Transistor with doped gate dielectric

Details Transistor with doped gate dielectric Transistor with doped gate dielectric

2008-05-06

2008-05-06

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S289000, C438S514000, C438S542000, C257SE21180, C257SE21210, C257SE21423

Reexamination Certificate

active

07368356

ABSTRACT:
A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal processes used to manufacture the transistor, dopant species from the doped region of the workpiece are outdiffused into the gate dielectric, creating a doped gate dielectric. The dopant species fill vacancies in the atomic structure of the gate dielectric, resulting in a transistor having increased speed, reduced power consumption, and improved voltage stability.

REFERENCES:
patent: 5108935 (1992-04-01), Rodder
patent: 5576226 (1996-11-01), Hwang
patent: 5596218 (1997-01-01), Soleimani et al.
patent: 5683934 (1997-11-01), Candelaria
patent: 5714788 (1998-02-01), Ngaoaram
patent: 5872387 (1999-02-01), Lyding et al.
patent: 5986287 (1999-11-01), Eberl et al.
patent: 6051865 (2000-04-01), Gardner et al.
patent: 6060755 (2000-05-01), Ma et al.
patent: 6100558 (2000-08-01), Krivokapic et al.
patent: 6110784 (2000-08-01), Gardner et al.
patent: 6261889 (2001-07-01), Ono
patent: 6291282 (2001-09-01), Wilk et al.
patent: 6303450 (2001-10-01), Park et al.
patent: 6358806 (2002-03-01), Puchner
patent: 6403976 (2002-06-01), Saitoh et al.
patent: 6472685 (2002-10-01), Takagi
patent: 6476454 (2002-11-01), Suguro
patent: 6492216 (2002-12-01), Yeo et al.
patent: 6498374 (2002-12-01), Ohuchi
patent: 6528851 (2003-03-01), Yu
patent: 6590271 (2003-07-01), Liu et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6696341 (2004-02-01), Sonoda
patent: 6699764 (2004-03-01), Tweet et al.
patent: 6774409 (2004-08-01), Baba et al.
patent: 6784101 (2004-08-01), Yu et al.
patent: 6815310 (2004-11-01), Roberds et al.
patent: 6815735 (2004-11-01), Inoue et al.
patent: 6821868 (2004-11-01), Cheng et al.
patent: 6916694 (2005-07-01), Hanafi et al.
patent: 2002/0011628 (2002-01-01), Takagi
patent: 2002/0125502 (2002-09-01), Baba et al.
patent: 2003/0102490 (2003-06-01), Kubo et al.
patent: 2003/0146473 (2003-08-01), Inoue et al.
patent: 2003/0148584 (2003-08-01), Roberds et al.
patent: 2004/0110336 (2004-06-01), King
patent: 2004/0221792 (2004-11-01), Forbes
patent: 2004/0232422 (2004-11-01), Forbes
patent: 2005/0035470 (2005-02-01), Ko et al.
patent: 2005/0139936 (2005-06-01), Li
patent: 2005/0145944 (2005-07-01), Murthy et al.
patent: 0 921 575 (1999-06-01), None
patent: 1 020 898 (2000-07-01), None
Chui, C.O., et al., “Germanium MOS Capacitors Incorporating Ultrathin High-k Gate Dielectric,” IEEE Electron Device Letters, Aug. 2002, pp. 473-475, vol. 23, No. 8, IEEE, Los Alamitos, CA.
Chui, C.O., et al., “A Sub-400° C. Germanium MOSFET Technology with High-k Dielectric and Metal Gate,” 2002, 4 pp., IEEE, Los Alamitos, CA.
Ernst, T., et al., “A New Si:C Epitaxial Channel nMOSFET Architecture with Improved Drivability and Short-Channel Characteristics,” 2003, 2 pp., 2003 Symposium on VLSI Technology Digest of Technical Papers.
“Front End Processes,” International Technology Roadmap for Semiconductors, 2002 Update, pp. 45-62, http://member.itrs.net/.
Höck, G., et al., “High Hole Mobility in Si0.17Ge0.83Channel Metal-Oxide-Semiconductor Field-Effect Transistors Grown by Plasma-Enhanced Chemical Vapor Deposition,” Applied Physics Letters, Jun. 26, 2000, pp. 3920-3922, vol. 76, No. 26, American Institute of Physics, College Park, MD.
Jiang, H., et al., “Electrical Properties of GeSi Surface- and Buried- Channel p-MOSFET's Fabricated by Ge Implantation,” IEEE Transactions on Electron Devices, Jan. 1996, pp. 97-103, vol. 43, No. 1, IEEE, Los Alamitos, CA.
John, S., et al., “Strained Sin-Channel Metal-Oxide-Semiconductor Transistor on Relaxed Si1-xGexFormed by Ion Implantation of Ge,” Applied Physics Letters, Apr. 5, 1999, pp. 2076-2078, vol. 74, No. 14, American Institute of Physics, College Park, MD.
King, A.C., et al., “Surface Proximity Effect on End-of-Range Damage of Low Energy Ge+Implantation,” Ultra Shallow Junctions 2003, Seventh International Workshop on: Fabrication, Characterization, and Modeling of Ultra-Shallow Doping Profiles in Semiconductors, Apr. 27-May 1, 2003, pp. 447-450, Santa Cruz, CA.
Lee, M.L., et al., “Strained Ge Channelp-Type Metal-Oxide-Semiconductor Field-Effect Transistors Grown on Si1-xGx/Si Virtual Substrates,” Applied Physics Letters, Nov. 12, 2001, pp. 3344-3346, vol. 79, No. 20, American Institute of Physics, College Park, MD.
Legoues, F.K., et al., “Oxidation Studies of SiGe,” Journal of Applied Physics, Feb. 15, 1989, pp. 1724-1728, vol. 65, No. 4, American Institute of Physics, College Park, MD.
Liu, K.C., et al., “A Deep Submicron Si1-xGex/Si Vertical PMOSFET Fabricated by Ge Ion Implantation,” IEEE Electron Device Letters, Jan. 1998, pp. 13-15, vol. 19, No. 1, IEEE, Los Alamitos, CA.
Nguyen, N.V., et al., “Characterization of the Interface Between Ge30-Implanted Crystalline Silicon and its Thermally Grown Oxide by Spectroscopic Ellipsometry,” Journal of Applied Physics, Jan. 15, 1990, pp. 599-603, vol. 67, No. 2, American Institute of Physics, College Park, MD.
Plummer, J.D., et al., “Silicon VLSI Technology: Fundamentals, Practice and Modeling,” 2000, p. 453, Prentice Hall, Upper Saddle River, NJ.
Qui{umlaut over (n)}ones, E., et al., “Enhanced Mobility PMOSFET's Using Tensile-Strained Si1-yCyLayers,” IEEE Electron Device Letters, Jul. 1999, pp. 338-340, vol. 20, No. 7, IEEE, Los Alamitos, CA.
Selvakumar, C.R., et al., “SiGe-Channel n-MOSFET by Germanium Implantation,” IEEE Electron Device Letters, Aug. 1991, pp. 444-446, vol. 12, No. 8, IEEE, Los Alamitos, CA.
Shang, H., et al., “High Mobility p-Channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric,” 2002, 4 pp., IEEE, Los Alamitos, CA.
Straube, U.N., et al., “Adverse Effect of Ge+Implantation for Fabrication of SiGe PMOS,” Electronics Letters, Dec. 6, 2001, pp. 1549-1550, vol. 37, No. 25.
Zollner, S., et al., “Optical Constants and Ellipsometric Thickness Determination of Strained Si1-xGex:C Layers on Si (100) and Related Heterostructures,” Journal of Applied Physics, Oct. 1, 2000, pp. 4102-4108, vol. 88, No. 7, American Institute of Physics, College Park, MD.
Inumiya, S., et al., “Fabrication of HfSiON Gate Dielectrics by Plasma Oxidation and Nitridation, Optimized for 65nm node Low Power CMOS Applications,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19, Document No. 4-89114-035-6/03.
Wolf, S., “Silicon Processing for the VLSI Era: Diffusion in Silicon” pp. 336-339.
“Front End Processes,” International Technology Roadmap for Semiconductor (ITRS), 2003 Edition, pp. 23-25, http://member.itrs.net/.

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