Semiconductor devices and method of fabrication

Details Semiconductor devices and method of fabrication Semiconductor devices and method of fabrication

2008-07-01

2008-07-01

Smith, Zandra (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S525000, C438S527000

Reexamination Certificate

active

07393752

ABSTRACT:
A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms the gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. The structure enables the manufacture of a deep submicron (<0.3 μm) power MOSFET using existing 0.13 μm process flow without additional masks and processing steps.

REFERENCES:
patent: 6599804 (2003-07-01), Bulucea et al.
patent: 2001/0019869 (2001-09-01), Hsu
Buti et al., “A New Asymmetrical Halo Source Gold Drain (HS-GOLD) Deep Sub-Half-Micrometer n-MOSFET Design for Reliability and Performance,” IEEE Transactions on Electron Devices, vol. 38, No. 8, Aug. 1991, pp. 1757-1764.

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