Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-03-22
2011-03-22
Thai, Luan C (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S259000, C438S262000
Reexamination Certificate
active
07910431
ABSTRACT:
On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the pMOS transistor. Thereafter, there is formed a single-layer wiring connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs.
REFERENCES:
patent: 4646425 (1987-03-01), Owens et al.
patent: 5292681 (1994-03-01), Lee et al.
patent: 5329228 (1994-07-01), Comeau
patent: 5977593 (1999-11-01), Hara
patent: 6122192 (2000-09-01), Furuhata et al.
patent: 6392268 (2002-05-01), Ishige
patent: 6731535 (2004-05-01), Ooishi et al.
patent: 7084437 (2006-08-01), Kitamura et al.
patent: 7202540 (2007-04-01), Komori et al.
patent: 2005/0230714 (2005-10-01), Komori et al.
patent: 2007/0114617 (2007-05-01), Komori et al.
patent: 2007/0117303 (2007-05-01), Komori et al.
patent: 5-504442 (1993-07-01), None
patent: 05-315922 (1993-11-01), None
patent: 10-32255 (1998-02-01), None
patent: 2001-015718 (2001-01-01), None
patent: 2004-95910 (2004-03-01), None
Japanese Office Action dated Jan. 6, 2009 issued in corresponding patent Application 2004-198888.
Japanese Office Action dated Jul. 1, 2008 issued in corresponding Application No. 2004-198888.
Patent Abstracts of Japan Publication No. 07183502 dated Jul. 21, 1995.
Patent Abstracts of Japan Publication No. 2002043446 dated Feb. 8, 2002.
Nakagawa Shin-ichi
Takahashi Koji
Fujitsu Semiconductor Limited
Thai Luan C
Westerman Hattori Daniels & Adrian LLP
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