Solving via-misalignment issues in interconnect structures...

Details Solving via-misalignment issues in interconnect structures... Solving via-misalignment issues in interconnect structures...

2011-01-11

2011-01-11

Zarneke, David A (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257SE23151

Reexamination Certificate

active

07868455

ABSTRACT:
An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and horizontally spaced apart from the conductive line by a space; and a filler dielectric material filling at least a portion of the space, wherein the filler dielectric material and the low-k dielectric region are formed of different materials. The integrated circuit structure further includes a capping layer over and adjoining the filler dielectric material and the low-k dielectric region. The filler dielectric material has a dielectric constant (k value) less than a k value of the capping layer.

REFERENCES:
patent: 6037249 (2000-03-01), Chiang et al.
patent: 6214719 (2001-04-01), Nag
patent: 6399476 (2002-06-01), Kim et al.
patent: 2005/0074961 (2005-04-01), Beyer et al.
patent: 2007/0178713 (2007-08-01), Jeng
patent: 101009266 (2007-08-01), None

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