Multiple-gate transistors formed on bulk substrates

Details Multiple-gate transistors formed on bulk substrates Multiple-gate transistors formed on bulk substrates

2011-01-04

2011-01-04

Hu, Shouxiang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257S331000, C257SE29022, C257S302000, C257S350000, C257S351000, C257S353000, C257S623000

Reexamination Certificate

active

07863674

ABSTRACT:
In one aspect, the present invention teaches a multiple-gate transistor130that includes a semiconductor fin134formed in a portion of a bulk semiconductor substrate132. A gate dielectric144overlies a portion of the semiconductor fin134and a gate electrode146overlies the gate dielectric144. A source region138and a drain region140are formed in the semiconductor fin134oppositely adjacent the gate electrode144. In the preferred embodiment, the bottom surface150of the gate electrode146is lower than either the source-substrate junction154or the drain-substrate junction152.

REFERENCES:
patent: 5893741 (1999-04-01), Huang
patent: 6252284 (2001-06-01), Muller et al.
patent: 6342410 (2002-01-01), Yu
patent: 6391695 (2002-05-01), Yu
patent: 6391782 (2002-05-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6432829 (2002-08-01), Muller et al.
patent: 6451656 (2002-09-01), Yu et al.
patent: 6475890 (2002-11-01), Yu
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6720619 (2004-04-01), Chen et al.
patent: 6764884 (2004-07-01), Yu et al.
patent: 6885055 (2005-04-01), Lee
patent: 6992354 (2006-01-01), Nowak et al.
patent: 2005/0035415 (2005-02-01), Yeo et al.
Huang, X., et al. “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Yang, F.-L., et al. “35nm CMOS FinFETs,” 2002 Symposium on VLSI Technology Digest of Technical Papers, Jun. 2002, pp. 109-110.
Wong, H.-S.P. “Beyond the Conventional Transistor,” IBM Journal of Research and Development, Mar./May 2002, pp. 133-167.
Chau, R. et al. “Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate,” Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials, Sep. 2002, pp. 68-69.
Yang, F.-L, et al. “25nm CMOS Omega FETs,” International Electron Devices Meeting, Digest of Technical Papers, Dec. 2002, pp. 255-258.
Colinge, J.P., et al. “Silicon-on-Insulator” “Gate-All-Around Device,” International Electron Devices Meeting, Dec. 1990, pp. 595-598.
Leobandung, E., et al., “Wire-Channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects.” Journal of Vacuum Science and Technology, vol. B15, No. 6, (Nov./Dec. 1997) pp. 2791-2794.

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