Memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds

Reexamination Certificate

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C257S686000, C257SE23024

Reexamination Certificate

active

07875985

ABSTRACT:
A memory device comprising at least one memory stack of stacked memory dies which are staggered with respect to each other,each stacked memory die of said memory stack comprising along its edge die pads for bonding said stacked memory die to substrate pads of said memory device connectable to a control circuit,wherein each die pad of a stacked memory die which connects said memory die individually to said control circuit comprises an increased distance (di) in comparison to die pads of said stacked memory die which connect said stacked memory die in parallel with corresponding die pads of other stacked memory dies of said memory stack to said control circuit.

REFERENCES:
patent: 5818114 (1998-10-01), Pendse et al.
patent: 5951304 (1999-09-01), Wildes et al.
patent: 6323548 (2001-11-01), Hiraga
patent: 6376904 (2002-04-01), Haba et al.
patent: 6476506 (2002-11-01), O'Connor et al.
patent: 6731011 (2004-05-01), Verma et al.
patent: 6900528 (2005-05-01), Mess et al.
patent: 2005/0093167 (2005-05-01), Saeki
German Office Action dated Aug. 24, 2007.

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