Spacer-less transistor integration scheme for high-K gate...

Details Spacer-less transistor integration scheme for high-K gate... Spacer-less transistor integration scheme for high-K gate...

2011-06-07

2011-06-07

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S291000, C438S301000, C257SE21429

Reexamination Certificate

active

07955919

ABSTRACT:
A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

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