Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-03-08
2011-03-08
Ghyka, Alexander G (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C257SE21576
Reexamination Certificate
active
07902067
ABSTRACT:
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
REFERENCES:
patent: 3030877 (1962-04-01), McDuffe
patent: 3849270 (1974-11-01), Takagi
patent: 3953625 (1976-04-01), Quaintance
patent: 4300184 (1981-11-01), Colla
patent: 4670091 (1987-06-01), Thomas
patent: 4685998 (1987-08-01), Quinn
patent: 4753896 (1988-06-01), Matloubian
patent: 4789647 (1988-12-01), Peters
patent: 4939568 (1990-07-01), Kato et al.
patent: 5046161 (1991-09-01), Takada
patent: 5055907 (1991-10-01), Jacobs
patent: 5061985 (1991-10-01), Meguro et al.
patent: 5106461 (1992-04-01), Volfson
patent: 5108950 (1992-04-01), Wakabayashi
patent: 5111276 (1992-05-01), Hingarh
patent: 5118369 (1992-06-01), Shamir
patent: 5212403 (1993-05-01), Nakanishi
patent: 5226232 (1993-07-01), Boyd
patent: 5227012 (1993-07-01), Brandli
patent: 5244833 (1993-09-01), Gansauge et al.
patent: 5300461 (1994-04-01), Ting
patent: 5346738 (1994-09-01), Samonides
patent: 5372967 (1994-12-01), Sundaram
patent: 5395137 (1995-03-01), Kim
patent: 5416356 (1995-05-01), Staudinger
patent: 5461333 (1995-10-01), Condon et al.
patent: 5461545 (1995-10-01), Leroy
patent: 5478773 (1995-12-01), Dow
patent: 5479049 (1995-12-01), Aoki
patent: 5481205 (1996-01-01), Frye et al.
patent: 5501006 (1996-03-01), Gehman, Jr.
patent: 5532512 (1996-07-01), Fillion
patent: 5534465 (1996-07-01), Frye
patent: 5576680 (1996-11-01), Ling
patent: 5635767 (1997-06-01), Wenzel
patent: 5641997 (1997-06-01), Ohta
patent: 5644102 (1997-07-01), Rostoker
patent: 5665989 (1997-09-01), Dangelo
patent: 5686764 (1997-11-01), Fulcher
patent: 5691248 (1997-11-01), Cronin
patent: 5701666 (1997-12-01), DeHaven
patent: 5731945 (1998-03-01), Bertin et al.
patent: 5767010 (1998-06-01), Mis et al.
patent: 5780930 (1998-07-01), Malladi et al.
patent: 5789303 (1998-08-01), Leung
patent: 5792594 (1998-08-01), Brown
patent: 5807791 (1998-09-01), Bertin et al.
patent: 5818110 (1998-10-01), Cronin
patent: 5818748 (1998-10-01), Bertin et al.
patent: 5827776 (1998-10-01), Bandyopadhyay
patent: 5827778 (1998-10-01), Yamada
patent: 5854513 (1998-12-01), Kim
patent: 5883435 (1999-03-01), Geffken
patent: 5884990 (1999-03-01), Burghartz
patent: 5892273 (1999-04-01), Iwasaki et al.
patent: 5910020 (1999-06-01), Yamada
patent: 5929508 (1999-07-01), Delgado
patent: 5952726 (1999-09-01), Liang
patent: 5953626 (1999-09-01), Hause
patent: 5955762 (1999-09-01), Hively
patent: 5970321 (1999-10-01), Hively
patent: 5994766 (1999-11-01), Shenoy
patent: 6008060 (1999-12-01), Chang
patent: 6008102 (1999-12-01), Alford
patent: 6011314 (2000-01-01), Leibovitz
patent: 6020640 (2000-02-01), Efland et al.
patent: 6022792 (2000-02-01), Ishii
patent: 6025275 (2000-02-01), Efland et al.
patent: 6030877 (2000-02-01), Lee
patent: 6031293 (2000-02-01), Hsuan et al.
patent: 6040604 (2000-03-01), Lauvray et al.
patent: 6075290 (2000-06-01), Schaefer et al.
patent: 6077726 (2000-06-01), Mistry
patent: 6100548 (2000-08-01), Nguyen
patent: 6117782 (2000-09-01), Lukanc
patent: 6121092 (2000-09-01), Liu
patent: 6130457 (2000-10-01), Yu et al.
patent: 6146958 (2000-11-01), Zhao
patent: 6147857 (2000-11-01), Worley
patent: 6159773 (2000-12-01), Lin
patent: 6168974 (2001-01-01), Chang
patent: 6180426 (2001-01-01), Lin
patent: 6184143 (2001-02-01), Ohashi
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6200888 (2001-03-01), Ito et al.
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6232147 (2001-05-01), Matsuki et al.
patent: 6232656 (2001-05-01), Yabu et al.
patent: 6271127 (2001-08-01), Liu
patent: 6288447 (2001-09-01), Amishiro
patent: 6294425 (2001-09-01), Hideki
patent: 6306749 (2001-10-01), Lin
patent: 6359328 (2002-03-01), Dubin
patent: 6362087 (2002-03-01), Wang
patent: 6383916 (2002-05-01), Lin
patent: 6416958 (2002-07-01), Vidovic
patent: 6429120 (2002-08-01), Ahn
patent: 6455885 (2002-09-01), Lin
patent: 6459135 (2002-10-01), Basteres et al.
patent: 6465879 (2002-10-01), Taguchi
patent: 6472745 (2002-10-01), Iizuka
patent: 6495442 (2002-12-01), Lin et al.
patent: 6509267 (2003-01-01), Woo
patent: 6515369 (2003-02-01), Lin
patent: 6518092 (2003-02-01), Kikuchi
patent: 6544880 (2003-04-01), Akram
patent: 6578754 (2003-06-01), Tung
patent: 6614091 (2003-09-01), Downey
patent: 6617681 (2003-09-01), Bohr
patent: 6636139 (2003-10-01), Tsai
patent: 6639299 (2003-10-01), Aoki
patent: 6646347 (2003-11-01), Mercado
patent: 6653563 (2003-11-01), Bohr
patent: 6680544 (2004-01-01), Lu
patent: 6683380 (2004-01-01), Efland et al.
patent: 6707124 (2004-03-01), Wachtler
patent: 6734563 (2004-05-01), Lin
patent: 6759275 (2004-07-01), Lee
patent: 6780748 (2004-08-01), Yamaguchi
patent: 6798073 (2004-09-01), Lin
patent: 6861740 (2005-03-01), Hsu
patent: 6943440 (2005-09-01), Kim
patent: 6963136 (2005-11-01), Shinozaki
patent: 7230340 (2007-06-01), Lin
patent: 7239028 (2007-07-01), Anzai
patent: 7265047 (2007-09-01), Lin
patent: 7271489 (2007-09-01), Lin
patent: 7309920 (2007-12-01), Lin
patent: 7372161 (2008-05-01), Lin
patent: 7382052 (2008-06-01), Lin
patent: 7446035 (2008-11-01), Lin et al.
patent: 7479450 (2009-01-01), Lin et al.
patent: 2001/0051426 (2001-12-01), Pozder
patent: 2002/0158334 (2002-10-01), Vu et al.
patent: 2003/0102551 (2003-06-01), Kikuchi
patent: 2003/0218246 (2003-11-01), Abe
patent: 2004/0023450 (2004-02-01), Katagiri
patent: 2004/0158758 (2004-08-01), Zarkesh
patent: 2006/0038231 (2006-02-01), Lin
patent: 2006/0049485 (2006-03-01), Pan
patent: 2006/0068574 (2006-03-01), Lin
patent: 2008/0003806 (2008-01-01), Lin et al.
patent: 2008/0006946 (2008-01-01), Lin
patent: 2008/0009131 (2008-01-01), Lin
patent: 2008/0042296 (2008-02-01), Lin
patent: 2008/0045002 (2008-02-01), Lin
patent: 2008/0045004 (2008-02-01), Lin
patent: 2008/0085596 (2008-04-01), Lin
patent: 2008/0085597 (2008-04-01), Lin
patent: 0831529 (1998-03-01), None
patent: 1 039 544 (2000-09-01), None
patent: 01135043 (1989-05-01), None
patent: 01183836 (1989-07-01), None
patent: 01184848 (1989-07-01), None
patent: 01184849 (1989-07-01), None
patent: 04316351 (1992-11-01), None
patent: 2000 216264 (2000-08-01), None
patent: 357449 (1999-05-01), None
“Processing Thick Multi level Poly imide Films for 3-D Stacked Memory”, by Michael D. Caterer et al., IEEE Trans. on Advanced Packaging, vol. 22, No. 2, May 1999, pp. 189-199.
“Power Distribution Techniques for VLSI Circuits”, by William S. Song et al., IEEE Jrnl. of Solid-State Circuits, vol. SC-21, No. 1, Feb. 1986, XP-002317942, pp. 150-156.
“Influence of the Series Resistance of On-Chip Power Supply Buses on Internal Device Failure After ESD Stress”, by H. Terletzki et al., XP 000413126, 1993 IEEE, vol. 40, No. 11, Nov. 1993, pp. 2081-2083.
Mistry, K. et al. “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (2007) pp. 247-250.
Edelstein, D.C., “Advantages of Copper Interconnects,” Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference (1995) pp. 301-307.
Theng, C. et al. “An Automated Tool Deployment for ESD (Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process,” IEEE International Conference on Semiconductor Electronics (2004) pp. 61-67.
Gao, X. et al. “An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance,” Solid-State Electronics, 27 (
Lee Jin-Yuan
Lin Mou-Shiung
Ghyka Alexander G
McDermott Will & Emery LLP
Megica Corporation
LandOfFree
Post passivation interconnection schemes on top of the IC chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Post passivation interconnection schemes on top of the IC chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Post passivation interconnection schemes on top of the IC chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2738446