Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-06-28
2011-06-28
Doan, Theresa T (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S201000, C438S266000, C257S314000, C257S315000
Reexamination Certificate
active
07968399
ABSTRACT:
Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
REFERENCES:
patent: 4369565 (1983-01-01), Muramatsu
patent: 5949101 (1999-09-01), Aritome
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6720610 (2004-04-01), Iguchi et al.
patent: 6768161 (2004-07-01), Kinoshita
patent: 6894930 (2005-05-01), Chien et al.
patent: 6906378 (2005-06-01), Sumino et al.
patent: 6939780 (2005-09-01), Yun et al.
patent: 6949447 (2005-09-01), Ahn et al.
patent: 7151295 (2006-12-01), Yaegashi et al.
patent: 7214580 (2007-05-01), Kitamura et al.
patent: 63-43321 (1988-02-01), None
patent: 3-220778 (1991-09-01), None
patent: 7-254652 (1995-10-01), None
patent: 8-125148 (1996-05-01), None
patent: 11-177066 (1999-07-01), None
patent: 11-317464 (1999-11-01), None
patent: 2001-93887 (2001-04-01), None
patent: 2001-168306 (2001-06-01), None
Peter VanDerVoom, et al., “CMOS Shallow-Trenc-Isolation to 50-nm Channel Widths”, IEEE Transactions on Electron Devices, vol. 47, No. 6, Jun. 2000, pp. 1175-1182.
Kitamura Yoshinori
Sugimoto Shigeki
Doan Theresa T
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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