Self-aligned complementary LDMOS

Details Self-aligned complementary LDMOS Self-aligned complementary LDMOS

2011-01-25

2011-01-25

Pham, Hoai v (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S545000, C257SE21427

Reexamination Certificate

active

07875517

ABSTRACT:
The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.

REFERENCES:
patent: 7141455 (2006-11-01), Hu et al.
patent: 7569884 (2009-08-01), Lee

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