Clock delay circuits and multiplexer connected to boundary...

Details Clock delay circuits and multiplexer connected to boundary... Clock delay circuits and multiplexer connected to boundary...

2011-06-07

2011-06-07

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C714S798000

Reexamination Certificate

active

07958420

ABSTRACT:
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

REFERENCES:
patent: 5682391 (1997-10-01), Narayanan
patent: 6286119 (2001-09-01), Wu et al.
patent: 2003/0101397 (2003-05-01), Whetsel, Jr.

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