Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2011-01-11
2011-01-11
Deo, Duy-Vu N. (Department: 1713)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S612000, C438S652000, C438S585000, C257SE21035, C257SE21314
Reexamination Certificate
active
07867911
ABSTRACT:
A method for forming a pattern in a semiconductor device includes forming an etch target layer, forming a hard mask over the etch target layer, the hard mask including a multiple-layer stack structure comprising a bottom layer, a transformed layer, and an upper layer, wherein the transformed layer is formed by transforming a surface of the bottom layer. The hard mask and the etch target layer are etched.
REFERENCES:
patent: 6593233 (2003-07-01), Miyazaki et al.
patent: 7084071 (2006-08-01), Dakshina-Murthy et al.
patent: 2004/0023475 (2004-02-01), Bonser et al.
patent: 2006/0231524 (2006-10-01), Liu et al.
patent: 2006/0240188 (2006-10-01), Fuss et al.
patent: 2003-0096765 (2003-12-01), None
patent: 10-2004-0057434 (2004-07-01), None
patent: 10-2004-0057502 (2004-07-01), None
patent: 10-2005-0019905 (2005-03-01), None
patent: 10-2006-0010932 (2006-02-01), None
Han Ky-Hyun
Nam Ki-Won
Blakely & Sokoloff, Taylor & Zafman
Dahimene Mahmoud
Deo Duy-Vu N.
Hynix / Semiconductor Inc.
LandOfFree
Method for forming pattern using hard mask does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming pattern using hard mask, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming pattern using hard mask will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2729763