Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-01-18
2011-01-18
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S305000, C438S595000, C257SE21177, C257SE21235, C257SE21429
Reexamination Certificate
active
07871914
ABSTRACT:
A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.
REFERENCES:
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5270257 (1993-12-01), Shin
patent: 5985126 (1999-11-01), Bleck et al.
patent: 6187651 (2001-02-01), Oh
patent: 6188104 (2001-02-01), Choi et al.
patent: 6255202 (2001-07-01), Lyons et al.
patent: 6303448 (2001-10-01), Chang et al.
patent: 6319777 (2001-11-01), Hueting et al.
patent: 6358800 (2002-03-01), Tseng
patent: 6642130 (2003-11-01), Park
patent: 6762105 (2004-07-01), Park
patent: 6884677 (2005-04-01), Kim
patent: 7012014 (2006-03-01), Lin et al.
patent: 04-093080 (1992-03-01), None
patent: 1020000019080 (2000-04-01), None
patent: 1020010064328 (2001-07-01), None
Notice to File a Response/Amendment to the Examination Report, Korean Application No. 10-2002-0081091, Nov. 22, 2004.
Choe Jeong-Dong
Kim Seong-Ho
Kim Sung-Min
Lee Chang-Sub
Lee Shin-Ae
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
Thomas Toniae M
Wilczewski Mary
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