IEEE 1149.1 and P1500 test interfaces combined circuits and...

Details IEEE 1149.1 and P1500 test interfaces combined circuits and... IEEE 1149.1 and P1500 test interfaces combined circuits and...

2011-01-25

2011-01-25

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

07877658

ABSTRACT:
In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

REFERENCES:
patent: 6393081 (2002-05-01), Whetsel
patent: 6442092 (2002-08-01), Tomita
patent: 2003/0131296 (2003-07-01), Park et al.
Kuen-Jong Lee; Cheng-I Huang; , “A hierarchical test control architecture for core based design,” Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian , vol., No., pp. 248-253, 2000 doi: 10.1109/ATS.2000.893633.
Bhattacharya, D.; , “Hierarchical test access architecture for embedded cores in an integrated circuit,” VLSI Test Symposium, 1998. Proceedings. 16th IEEE , vol., No., pp. 8-14, Apr. 26-30, 1998 doi: 10.1109/VTEST.1998.670842.

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