Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2011-01-11
2011-01-11
Gu, Shawn X (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S005000, C711S105000, C711S167000, C711S169000, C711SE12001
Reexamination Certificate
active
07870351
ABSTRACT:
Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.
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Gu Shawn X
Micro)n Technology, Inc.
TraskBritt
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