Semiconductor memory device with bit line of small...

Details Semiconductor memory device with bit line of small... Semiconductor memory device with bit line of small...

2011-07-26

2011-07-26

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S314000, C257SE21679, C438S262000

Reexamination Certificate

active

07985648

ABSTRACT:
A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.

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Office Action dated May 26, 2006.
Japanese Office Action, with partial English translation, issued in Japanese Patent Application No. 2003-287831, mailed Jun. 15, 2010.

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