Semiconductor devices with sidewall conductive patterns and...

Details Semiconductor devices with sidewall conductive patterns and... Semiconductor devices with sidewall conductive patterns and...

2011-07-05

2011-07-05

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27103, C257SE29300, C438S211000

Reexamination Certificate

active

07973354

ABSTRACT:
A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

REFERENCES:
patent: 4780431 (1988-10-01), Maggioni et al.
patent: 5023679 (1991-06-01), Shibata
patent: 6221717 (2001-04-01), Cremonesi et al.
patent: 7012295 (2006-03-01), Sato et al.
patent: 2004/0026748 (2004-02-01), Goda et al.
patent: 2000-164834 (2000-06-01), None
patent: 10-2002-0065113 (2002-08-01), None
Notice to File a Response/Amendment to the Examination Report, Korean Application No. 10-2004-0089435, Mar. 27, 2006.

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