Structure and process for a gouge-free stacked non-volatile memo

Details Structure and process for a gouge-free stacked non-volatile memo Structure and process for a gouge-free stacked non-volatile memo

1998-01-22

2000-12-19

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, H01L 21336

Patent

active

061626821

ABSTRACT:
A structure and process for a gouge-free substrate non-volatile memory cell with a floating gate, field effect transistor and a select gate transistor. The cell includes a floating gate, field effect transistor and a select gate transistor wherein the select gate transistor comprises a first conductive layer covered by a second conductive layer wherein electrical contact is made to the first conductive layer. The invention contemplates that the first and second conductive layers can be separated by an insulative layer. The invention also contemplates that the first and second conductive layers may be of different cross-sectional areas, wherein the cross-sectional area of the first conductive layer is larger than the cross-sectional area of the second conductive layer and wherein electrical contact is made to the first conductive layer at a sight not encompassed or covered by the second conductive layer. Also presented is a process of construction of peripheral die circuits comprised of two conductive layers similar to the select gate of the non-volatile memory cell or comprised of second conductive layer material.

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