Semiconductor device

Details Semiconductor device Semiconductor device

2011-01-25

2011-01-25

Geyer, Scott B (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

Reexamination Certificate

active

07875986

ABSTRACT:
Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.

REFERENCES:
patent: 5153710 (1992-10-01), McCain
patent: 6437990 (2002-08-01), Degani et al.
patent: 6921981 (2005-07-01), Tien
patent: 2003/0117832 (2003-06-01), Tomishima
patent: 2005/0253236 (2005-11-01), Nakayama
patent: 8-181247 (1996-07-01), None
patent: 2000-243893 (2000-09-01), None
patent: 2005-117062 (2005-04-01), None
patent: 2005-317830 (2005-11-01), None
patent: 2005-322814 (2005-11-01), None
Japanese Office Action dated Jun. 18, 2008, with English language translation.

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