Process for creating vias using pillar technology

Details Process for creating vias using pillar technology Process for creating vias using pillar technology

1996-06-13

1998-09-01

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438631, 438669, 438637, H01L 2144

Patent

active

058010939

ABSTRACT:
A process for creating metal pillar via structures, used to interconnect multilevel metallizations, has been developed. The process features the creation of a via hole, in a thin dielectric layer, exposing the top surface of an underlying first level metallization structure. The metal pillar via structure is next formed, contacting the first level metallization structure, exposed in the opened via hole in the thin dielectric layer. The spaces between the metal pillar via structures are filled with a composite dielectric material, featuring a spin on glass layer, which provides partial planarazation. The planarazation process is completed via a chemical mechanical polishing process, which also exposes the top surface of the metal pillar via structure, making the metal pillar via structure easily accessible for contact for subsequent, overlying metallization structures.

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patent: 4917759 (1990-04-01), Fisher et al.
patent: 5262354 (1993-11-01), Cote et al.
patent: 5312512 (1994-05-01), Allman et al.
patent: 5616519 (1997-04-01), Ping
patent: 5639692 (1997-06-01), Teong
patent: 5663108 (1997-09-01), Lin

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