Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-06-21
2011-06-21
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
07966533
ABSTRACT:
Various systems and methods for registering data are disclosed herein. For example, test enabled flip-flop devices are provided. Such devices include a test mode input signal and a register output signal. In addition, the devices include a flip-flop with a data input and a clock input. When the test mode input signal is de-asserted, the flip-flop is operable to register the data input upon a transition of the clock input. Further, the registered data input signal is provided as the register output signal. The devices also include a test circuit with a test data input. The test circuit is operable to provide the test data input signal as the register output signal when the test mode input signal is asserted.
REFERENCES:
patent: 5719878 (1998-02-01), Yu et al.
patent: 6499123 (2002-12-01), McFarland et al.
Brady III Wade J.
Gaffin Jeffrey A
McMahon Daniel F
Patti John J.
Telecky , Jr. Frederick J.
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