Method of fabricating a flash memory device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257S314000, C257SE21691, C257SE21683

Reexamination Certificate

active

07919369

ABSTRACT:
In a method of fabricating a flash memory device, a lower capping conductive layer of a peri region is patterned. A step formed between a cell gate and a gate for a peri region transistor is decreased by controlling a target etch thickness of a hard mask. Thus, an impurity does not infiltrate into the bottom of the gate for the peri region transistor through a lost portion of a SAC nitride layer. Accordingly, a hump phenomenon of the transistor formed in the peri region can be improved. Furthermore, a leakage current characteristic of the transistor formed in the peri region can be improved.

REFERENCES:
patent: 7436017 (2008-10-01), Lee et al.
patent: 7476928 (2009-01-01), Kim
patent: 7598564 (2009-10-01), Kang et al.
patent: 100273705 (2000-04-01), None
patent: 1020010061513 (2001-07-01), None
patent: 1020010108988 (2001-12-01), None
patent: 1020020095689 (2002-12-01), None

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