Register selection circuitry receiving select signals from...

Details Register selection circuitry receiving select signals from... Register selection circuitry receiving select signals from...

2011-08-16

2011-08-16

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

08001435

ABSTRACT:
A TAP linking module (21, 51) permits plural TAPs (TAPs1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

REFERENCES:
patent: 4918379 (1990-04-01), Jongepier
patent: 5056093 (1991-10-01), Whetsel
patent: 5627842 (1997-05-01), Brown et al.
patent: 5819025 (1998-10-01), Williams
patent: 6539497 (2003-03-01), Swoboda et al.
Ruparel, K.N.; Chin, C.; Fitzgerald, J.; , “A vertically integrated test methodology based on JTAG IEEE 1149.1 Standard Interface,” ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International , vol., No., pp. P11-4/1-4, Sep. 23-27, 1991 doi: 10.1109/ASIC.1991.242912.

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