Test entry circuit and method for generating test entry signal

Details Test entry circuit and method for generating test entry signal Test entry circuit and method for generating test entry signal

2011-05-24

2011-05-24

Beausoliel, Robert (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S720000

Reexamination Certificate

active

07949923

ABSTRACT:
Test entry circuit and method for generating test entry signal including a first source signal generator configured to receive a test signal through a pad to generate a first mode source signal for a first test mode, a second source signal generator configured to count activation transitions of the test signal to generate a second mode source signal for a second test mode and an entry signal generator configured to receive the first and second mode source signals to generate a first test mode entry signal for entering the first test mode and a second test mode entry signal for entering the second test mode.

REFERENCES:
patent: 2003/0126529 (2003-07-01), Cho
patent: 1999-005719 (1999-01-01), None
patent: 1020000027556 (2000-05-01), None
patent: 1020030027317 (2003-04-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Jan. 29, 2010.
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Apr. 21, 2009 with an English Translation.

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