Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-02-01
2011-02-01
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
07882411
ABSTRACT:
To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation unit circuits and a control unit circuit. The control unit circuit specifies the operation period of the corresponding circuit block on the basis of the input and output signals of the shift register unit circuits and supplies a clock signal and an inverted clock signal to the shift register unit circuit.
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Gaffin Jeffrey A
McMahon Daniel F
Oliff & Berridg,e PLC
Seiko Epson Corporation
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