Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-02-15
2011-02-15
Landau, Matthew C (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S219000, C438S222000, C438S424000, C438S459000, C257SE21564
Reexamination Certificate
active
07888197
ABSTRACT:
A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX”) layer including a layer of doped silicate glass. A sacrificial stressed layer is deposited onto the SOI substrate to overlie the SOI layer. Trenches are then etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften and the sacrificial stressed layer to relax, to thereby apply a stress to the SOI layer to form a stressed SOI layer. The trenches in the stressed SOI layer are then filled with a dielectric material to form trench isolation regions contacting peripheral edges of the stressed SOI layer, the trench isolation regions extending downwardly from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer is then removed to expose the stressed SOI layer. Field effect transistors can then be formed in the stressed SOI layer.
REFERENCES:
patent: 4771016 (1988-09-01), Bajor et al.
patent: 5152834 (1992-10-01), Allman
patent: 5543648 (1996-08-01), Miyawaki
patent: 6214702 (2001-04-01), Kim
patent: 6218289 (2001-04-01), Wu
patent: 6225154 (2001-05-01), Allman
patent: 6878611 (2005-04-01), Sadana et al.
patent: 6991998 (2006-01-01), Bedell et al.
patent: 7125759 (2006-10-01), Chen et al.
patent: 7202513 (2007-04-01), Chidambarrao et al.
patent: 7223994 (2007-05-01), Chidambarrao et al.
patent: 7384829 (2008-06-01), Cheng et al.
patent: 7416965 (2008-08-01), Mantl et al.
patent: 7449379 (2008-11-01), Ochimizu et al.
patent: 7482252 (2009-01-01), Wu et al.
patent: 7632724 (2009-12-01), Chidambarrao et al.
patent: 2002/0140031 (2002-10-01), Rim
patent: 2003/0003708 (2003-01-01), Ireland
patent: 2004/0094763 (2004-05-01), Agnello et al.
patent: 2004/0194812 (2004-10-01), Matsuno et al.
patent: 2004/0262784 (2004-12-01), Doris et al.
patent: 2005/0054175 (2005-03-01), Bauer
patent: 2005/0064646 (2005-03-01), Chidambarrao et al.
patent: 2005/0079449 (2005-04-01), Kwon et al.
patent: 2005/0104131 (2005-05-01), Chidambarrao et al.
patent: 2005/0269561 (2005-12-01), Chidambarrao et al.
patent: 2006/0001089 (2006-01-01), Bedell et al.
patent: 2006/0068545 (2006-03-01), Goldbach
patent: 2006/0125008 (2006-06-01), Chidambarrao et al.
patent: 2006/0128117 (2006-06-01), Ghyselen et al.
patent: 2006/0214232 (2006-09-01), Chen et al.
patent: 2007/0059875 (2007-03-01), Mishima
patent: 2007/0069294 (2007-03-01), Chidambarrao et al.
patent: 2007/0087525 (2007-04-01), Chen et al.
patent: 2007/0096195 (2007-05-01), Hoentschel et al.
patent: 2007/0122965 (2007-05-01), Chidambarrao et al.
patent: 2007/0158753 (2007-07-01), Arnold et al.
patent: 2007/0235807 (2007-10-01), White et al.
patent: 2007/0238233 (2007-10-01), Sadaka et al.
patent: 2007/0269963 (2007-11-01), Cheng et al.
patent: 2007/0278574 (2007-12-01), Hsu et al.
patent: 2008/0135875 (2008-06-01), Agnello et al.
patent: 2008/0191281 (2008-08-01), Chidambarrao et al.
patent: 2008/0237709 (2008-10-01), Chidambarrao et al.
patent: 2008/0303091 (2008-12-01), Shimizu et al.
patent: 05160089 (1993-06-01), None
U.S. Appl. No. 11/548,428, entitled “Method of Reducing Stacking Faults Through Annealing”, of Yun-Yu Wang et al., filed Oct. 11, 2006.
Chidambarrao Dureseti
Henson William K.
Liu Yaocheng
International Business Machines - Corporation
Landau Matthew C
Neff Daryl K.
Nicely Joseph C
Schnurmann H. Daniel
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