Circuit arrangement and method of testing an application...

Details Circuit arrangement and method of testing an application... Circuit arrangement and method of testing an application...

2011-01-11

2011-01-11

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S733000

Reexamination Certificate

active

07870453

ABSTRACT:
According to an example embodiment, there is an integrated circuit arrangement with at least one application circuit to be tested, and with at least one self-test circuit for testing the application circuit and generating at least one pseudo-random test sample. wherein said The pseudo-random test sample is converted into at least one test vector that is programmable and/or deterministic and is supplied to the application circuit for testing purposes via at least one logic gate and at least one signal that is applied to said logic gate. The output signal arising in dependence on the deterministic test vector is evaluated by the application circuit by at least one signature register. Furthermore, there is a method of testing the application circuit such that Built In Self Test (BIST) hardware connected to the additional deterministic logic is reduced; it is suggested that the signal supplied to the logic gate is made available by a Bit Flipping Function (BFF) logic circuit based on at least one self-test circuit.

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