Semiconductor memory device and method for operating the same

Details Semiconductor memory device and method for operating the same Semiconductor memory device and method for operating the same

2011-02-22

2011-02-22

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233500

Reexamination Certificate

active

07894278

ABSTRACT:
A semiconductor device includes a plurality of input units configured to receive a plurality of data, a plurality of latching units configured to latch output signals of the plurality of input units in response to a plurality of synchronization clock signals, and a synchronization clock generating unit configured to delay a source clock signal by a time corresponding to each of signal transmission times taken between the plurality of input units and the plurality of latching units, thereby generating the plurality of synchronization clock signals.

REFERENCES:
patent: 6556505 (2003-04-01), Tojima et al.
patent: 6597627 (2003-07-01), Arata et al.
patent: 6707727 (2004-03-01), Tamura et al.
patent: 6735732 (2004-05-01), Yamada
patent: 1020050062842 (2005-06-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Jul. 30, 2009 with an English Translation.

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