Memory structure with word line buffers

Details Memory structure with word line buffers Memory structure with word line buffers

2011-02-01

2011-02-01

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189110, C365S230060, C365S148000, C365S163000

Reexamination Certificate

active

07881126

ABSTRACT:
A memory comprises a plurality of memory cells. A row decoder module selectively drives word lines using a voltage level to access selected ones of the memory cells. A first regeneration module selectively pulls the voltage level on one of the word lines to one of first and second predetermined voltage levels. At least one of the memory cells of the one of the word lines is located between the first regeneration module and the row decoder module.

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Notification of Transmittal of the International Search Report and The Written Opinion of the International Searching Authority, or the Declaration dated Nov. 6, 2008 in reference to PCT/US2008/065050.

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