Scan test circuit and scan test control method

Details Scan test circuit and scan test control method Scan test circuit and scan test control method

2011-05-10

2011-05-10

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

07941720

ABSTRACT:
A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a shift operation mode when an output of the control FF is a first status value, and in a normal operation mode when the output is a second status value. When the control signal is switched from the first status value to the second status value, the control FF outputs the second status value to multiple scan storage elements synchronously with a first clock pulse, after the switching, of a clock provided to multiple scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control FF outputs the first status value to multiple scan storage elements at a timing of the control signal switching.

REFERENCES:
patent: 7155649 (2006-12-01), Nakao et al.
patent: 2002/0162065 (2002-10-01), Kashiwagi
patent: 2003/0080750 (2003-05-01), Parker et al.
patent: 2005/0235184 (2005-10-01), Yamauchi
patent: 2004-294424 (2004-10-01), None

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