Stacked memory cell for use in high-density CMOS SRAM

Details Stacked memory cell for use in high-density CMOS SRAM Stacked memory cell for use in high-density CMOS SRAM

2011-04-12

2011-04-12

Le, Vu A (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S174000, C365S168000

Reexamination Certificate

active

07924604

ABSTRACT:
A stacked memory cell for use in a high-density static random access memory is provided that includes first and second pull-down transistors formed in a first layer, a pass transistor connected between a gate of the second pull-down transistor and a bit line and formed in the first layer and a first and second pull-up transistors formed in a second layer located above the first layer and connected with the first and second pull-down transistors respectively to form an inverter latch. With the construction of a stacked memory cell having a lone pass transistor, cell size is reduced compared to a conventional six-transistor cell, and driving performance of the pass transistor can be improved.

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