Interconnections for plural and hierarchical P1500 test...

Details Interconnections for plural and hierarchical P1500 test... Interconnections for plural and hierarchical P1500 test...

2011-03-22

2011-03-22

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07913135

ABSTRACT:
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores.-The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

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Bhattacharya, D.; , “Hierarchical test access architecture for embedded cores in an integrated circuit,” VLSI Test Symposium, 1998. Proceedings. 16th IEEE , vol., no., pp. 8-14, Apr. 26-30, 1998 doi: 10.1109/VTEST.1998.670842 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=670842&isnumber=14777.

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