Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-05-03
2011-05-03
Picardat, Kevin M (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S186000, C438S364000, C438S369000, C438S514000, C438S527000, C438S542000
Reexamination Certificate
active
07935601
ABSTRACT:
A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500° C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.
REFERENCES:
patent: 5953632 (1999-09-01), Matsubara
patent: 6168983 (2001-01-01), Rumennik et al.
patent: 2009/0176343 (2009-07-01), Shima et al.
D.M. Brown et al entitled “Silicon Carbide MOSFET Integrated Circuit Technology” published in Physica Status Solidi (a), vol. 162, No. 1, pp. 459-479, Jul. 1997.
P.G. Neudeck et al entitled “Stable Electrical Operation of 6H-Si JFET's and IC's for Thousands of Hours at 500° C” published in IEEE Electron Device Letters, vol. 29, No. 5, May 2008.
P.G. Neudeck et al entitled “6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500° C” published in Proceedings 2008, IMAPS International High Temperatures Electronics Conference, pp. 95-102, May 2008.
Richard C. Jaeger “Volume V Introduction to Microelectronic Fabrication” published as part of the Modular Services on Solid State Devices by Addison-Wesley Publishing, Reading, MA 1988.
P.G. Neudeck, G.M. Beheim, and C.S. Salupo, entitled “600° C Logic Gates Using Silicon Carbide JFETs” and published in Government Microcircuit Applications Conference Technical Digest, Anahiem, CA, 2000, pp. 421-424.
G.W. Neudeck entitled “The PN Junction Diode” given on pp. 75-82 thereof and published by Addison-Wesley Publishing 1989, Reading, MA.
D.J. Spry et al “Fabrication and Testing of 6H-SiC JFET for Prolonged 500° C Operation in Air Ambient” presented at the 2007 International Conference on Silicon Carbide and Related Materials, Oct. 15, 2007, and published in Materials Science Forum vols. 600-603, pp. 1079-1082, Sep. 2008.
P.G. Neudeck et al “Long Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operation at 500° C” presented at the Materials Research Society 2008 Spring Meeting, Mar. 25-27, 2008, San Francisco, CA, and published in Materials Research Society Symposium Proceedings, vol. 1069, pp. 209-214, Apr. 2008.
D.J. Spry et al “Electrical Operation of 6H-SiC MESFET at 500° C for 500 Hours in Air Ambient” published in Proceedings 2004 IMAPS International Conference Exhibition on High Temperature Electronics (HiTEC 2004), May 2004.
R.S. Okojie, D. Lukco, Y.L. Chen, and D.J. Spry, “Reliability Assessment of Ti/TaS12/Pt Ohmic Contacts on SiC after 1000 h at 600° C” published in the Journal of Applied Physics, vol. 91, No. 10, pp. 6553-9559, 2002.
Liang-Yu-Chen and Jih-Fen Lei “Packing of Harsh Environment MEMS Devices” contained in the MEMS Handbook (Second Editoion 2006) published by CRC Press, Boca Raton, Florida.
Philip G. Neudeck et al “Extreme Temperature 6H-SiC JFET Integrated Circuit Technology” published on-line Jun. 29, 2009 and will appear as a featured article of the Journal entitled Physica Status Solidi A.
Earp III Robert H.
Picardat Kevin M
Prasad Neil
The United States of America as represented by the Administrator
LandOfFree
Method for providing semiconductors having self-aligned ion... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for providing semiconductors having self-aligned ion..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for providing semiconductors having self-aligned ion... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2620732