Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-01
2001-11-20
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S365000
Reexamination Certificate
active
06320222
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a structure and method for reducing threshold voltage variations due to dopant fluctuations.
BACKGROUND OF THE INVENTION
The threshold voltage (V
t
) tolerance on metal-oxide semiconducting field effect transistor (MOSFET) is an important design parameter in very large scale integrated circuits (VLSI). The threshold voltage (V
t
) is contributed to mainly by variations in insulator charge, gate oxide thickness, short channel effect, narrow channel effect and macroscopic doping tolerance. The statistical total is typically in the vicinity of 200 mV. As the dimensions of MOSFET devices are reduced, constant field scaling dictates that the doping level within the channel increase in inverse proportion to the device dimension. This means that the number of dopant atoms within the device channel decreases in proportion to the square of the device dimensions. Device operation, dependent upon a forbidden energy gap within the silicon, free of sub-bands, requires that the location of dopant impurity ions within the silicon lattice be completely statiscally random. As the number of dopant ions within a device decreases, statistical fluctuations in the random placement of dopant ions will increase from device to device. Since the threshold voltage (V
t
) of a MOSFET strongly depends on the doping, threshold voltage tolerance due to statistical dopant density fluctuation similarly increases.
It has been shown that for a scaled device design point with a width to length equivalency of 0.1 &mgr;m, has an average number of 360 dopant ions within the channel. In a device with these dimensions, a one sigma threshold voltage (V
t
) tolerance is only 20 mV. In effect, as dimensions continue to decrease, threshold voltage (V
t
) tolerance in MOSFETs will not only become dominant, but will constitute a practical limit MOSFET dimensional scaling and device application. Also, in this environment, expanded applications for MOSFETs, e.g., in production drivers and clock drivers with uniform characteristics and delays, become especially difficult since circuit timing and delay times become critical as dimensions become smaller and the demand for circuit speeds increases.
One approach to overcoming statistical dopant density fluctuation is to provide a ground plane doping profile wherein a high doping region is buried beneath a near intrinsic layer at the device surface. Although this type of retrograde doping profile does reduce the sensitivity to the doping variations, it negatively increases the sensitivity to short channel effects.
A method to decrease the sensitivity to both doping fluctuations and channel length variations is to completely remove the impurity in the channel. This is accomplished by using intrinsic silicon on insulator (SOI) devices. However, the same requires both very thin silicon films of approximately 20 nanometers (nm) for device length of 0.1 &mgr;m, and an alternative means of controlling the threshold voltage (V
t
) other than by impurity doping. In other words, a processing technology change would be required with a departure from conventional processing tools and steps, or changing the gate material from polysilicon to a metal.
Thus, what is needed is a method and structure for MOSFETs which reduce or eliminate the effects of statistical dopant fluctuations and channel length variations as the dimensions in these devices continue to scale down. Further, it is desirable to develop a method and structure for MOSFETs which can accord these benefits using conventional processing tools and process steps.
SUMMARY OF THE INVENTION
The above mentioned problems with threshold voltage variations and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method which improves operational reliability and performance is provided.
In particular, an illustrative embodiment of the present invention includes a method of fabricating a transistor on a substrate. The method includes forming a first source/drain region on the substrate. A body region is vertically formed on the first source/drain region. Vertically forming the body region included vertically growing an epitaxial layer. The body region includes opposing sidewall surfaces. A second source drain region is formed on the body region. A first gate is formed on a first one of the opposing sidewall surfaces. And, the method further includes forming a second gate on a second one of the opposing sidewall surfaces.
Another embodiment of the present invention includes a method of fabricating a transistor on a substrate. The method includes forming a first conductivity type first source/drain region on the substrate. A second conductivity type body region is vertically formed on the first source/drain layer. Vertically forming the body region includes vertically growing an epitaxial layer. The body region includes opposing sidewall surfaces. A first conductivity type second source/drain region is formed on the body region layer. A first gate is formed on a first one of the opposing sidewall surfaces. And, a second gate is formed on a second one of the opposing sidewall surfaces.
In another embodiment, a method of fabricating a transistor on a substrate is provided. The method includes vertically forming a body region extending outwardly from the substrate. Vertically forming the body region includes forming the body region as a fully depleted structure. Vertically forming the body region includes forming the body region with opposing sidewall surfaces. A first source/drain region is formed adjacent to the body region. A second source/drain region is similarly formed adjacent to the body region. A first gate is formed on a first one of the opposing sidewall surfaces. Further, a second gate on a second one of the opposing sidewall surfaces.
In another embodiment of the present invention, a dual-gated transistor on a substrate is provided. The dual-gated transistor includes a first source/drain region, a body region, and a second source/drain region. The body region has opposing sidewall surfaces and is a fully depleted structure. A first gate located on a first one of the opposing sidewall surfaces and a second gate located on a second one of the opposing sidewall surfaces. The dual-gated transistor is formed by forming a first source/drain region on the substrate, vertically forming a body region on the first source/drain by vertically growing an epitaxial layer, growing a second source/drain region on the body region, and forming first and second gates on a first and second one of the opposing sidewall surfaces respectively.
In another embodiment of the present invention, a dual-gated transistor on a substrate is provided. The dual-gated transistor includes a first source/drain region, a body region which has opposing sidewall surfaces, and a second source/drain region. The body region is a fully depleted structure. A first gate is located on a first one of the opposing sidewall surfaces. A second gate is located on a second one of the opposing sidewall surfaces. The dual-gated transistor is formed by vertically forming a body region extending outwardly from the substrate, forming a first source/drain region adjacent to the body region and similarly forming a second source/drain region adjacent to the body region. A first gate is formed on a first one of the opposing sidewall surfaces, and a second gate is formed on a second one of the opposing sidewall surfaces.
Thus, an improved method and structure are provided for MOSFETs which reduce or eliminate the effects of statistical dopant fluctuations. The device includes a dual-gated FET which can be fabricated according to a novel processing sequence using current fabrication line CMOS processing tolls and process procedures. Hence, the invention does not require any additional masks, forms, or number of process procedures. The dual-gated MOSFET has two gates one on
Forbes Leonard
Noble Wendell P.
Crane Sara
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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