Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-05
2001-11-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S622000
Reexamination Certificate
active
06319767
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating a metal-insulator-metal capacitor, and more particularly, to a method of forming a metal-insulator-metal capacitor without metal corner erosion in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitor matching for metal-insulator-metal (MIM) capacitors in RF mixed signal applications is increasingly critical owing to stringent requirements. Nevertheless, process-instigated issues present major obstacles to efficient capacitor matching. One major process-instigated issue is varying capacitor characteristics owing to different extents of top metal erosion during bottom metal electrode patterning. The size of the landing area for a contact array, especially around the metal corners can differ between MIM capacitors. Because of relatively poor etch selectivity between photoresist and metal, and because of thinner resist thickness lining the top metal electrode, especially along the sidewalls and top edges, the corners of the top metal electrode will be aggressively etched. This results in jagged edges at the top metal or corner rounding of the top metal electrode. The degree of etching or rounding differs from capacitor to capacitor and is uncontrollable. This makes capacitor matching for MIM in mixed signal applications difficult. It is desired to find a method to eliminate top metal corner shaping and also to attain better etch process control.
Co-pending U.S. patent application Ser. No. 09/726,655 to Cha et al, filed on Nov. 30, 2000, teaches another method to eliminate top metal corner shaping by forming spacers on the top metal electrode. The spacers provide a sloping contour for the photoresist so that photoresist thinning at the corners is avoided. U.S. Pat. No. 5,812,364 to Oku et al, 5,998,264 to Wu, 5,466,617 to Shannon, and 5,162,258 to Lemnios et al show various MIM capacitor processes.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-metal capacitor.
Another object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated.
Yet another object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated by patterning the top metal electrode after patterning the bottom metal electrode, which is used for making interconnection.
A further object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated by using plasma ashing and hard masking techniques.
A still further object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated and wherein only one masking step is required for patterning first the bottom metal electrode and second, the top metal electrode.
In accordance with the objects of this invention, a method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is achieved. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask. The second metal layer is patterned using the hard mask layer as an etching mask whereby the second metal layer forms a top electrode of the capacitor to complete fabrication of a metal-insulator-metal capacitor.
REFERENCES:
patent: 5162258 (1992-11-01), Lemnios et al.
patent: 5466617 (1995-11-01), Shannon
patent: 5812364 (1998-09-01), Oku et al.
patent: 5998264 (1999-12-01), Wu
patent: 6177351 (2001-01-01), Beratan et al.
Cha Randall Cher Liang
Chan Lap
Lee Tae Jong
Lim Yeow Kheng
See Alex
Chartered Semiconductor Manufacturing Ltd.
Le Thao P.
Nelms David
Pike Rosemary L. S.
Saile George O.
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