Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-16
2001-10-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000
Reexamination Certificate
active
06303449
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of MOS semiconductor device and more particularly to the fabrication of an elevated source/drain (S/D) for a field effect transistor.
2) Description of the Prior Art
In conventional CMOS processing, the active silicon regions are contacted through openings in the overlying oxide insulating layer. Metal used for forming electrical contacts must overlay these openings sufficiently to prevent damage to the active regions during patterning of the metal. Furthermore, the active source and drain regions must be large enough to accommodate misalignment during patterning. The dimensions of these active region result in large source/drain to substrate capacitances that seriously degrade the performance of the circuit. Furthermore, these conventional processing methods are unsuitable for fabricating devices of submicron size.
To overcome these problems, many schemes have been proposed to provide self-aligned source/drain contacts in submicron devices. These include various proposals for providing local interconnect layers, typically of TiN or polysilicon, to interface with a raised source and drain.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,804,846 (Fuller) that teaches a method for a self aligned elevated S/D by W layer and CMP.
U.S. Pat. No. 5,915,183 (Gambino et al.) shows a raised source/drain (S/D) process by a Poly etch.
U.S. Pat. No. 5,897,357 (Wu et al.) shows a process for a raised source/drain (S/D).
U.S. Pat. No. 5,422,289 (Pierce) shows another raised poly S/D process.
U.S. Pat. No. 6,015,727 (Wanlass) teaches a damascene S/D process.
However, the prior art process can be improved upon.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating an elevated source/drain (S/D).
It is an object of the present invention to provide a method for fabricating an elevated source/drain (S/D) that is more manufacturable than the prior art processes.
It is an object of the present invention to provide a method for fabricating a self aligned elevated source/drain (S/D) by the selective removal of gate dielectric in the source/drain region followed by poly deposition and chemical-mechanical polish (CMP).
It is an objective to provide a method to provide a shallow junction to minimize short Channel effects.
It is an objective to provide a method to provide a salicide process that does not cause junction leakage.
To accomplish the above objectives, the present invention provides a method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer has at least a gate opening and source/drain (S/D) openings adjacent to the gate opening. “Spacer portions” of the first insulating layer define the gate opening. A gate dielectric layer is formed over the substrate in the gate opening. A conductive layer is formed over the substrate. The conductive layer fills the gate opening and the source/drain (S/D) openings. The conductive layer is doped with dopants. The conductive layer is planarized to form a gate over the gate dielectric layer and filling the gate opening and filling the source/drain (S/D) opening to form elevated source/drain (S/D) regions. The conductive layer is preferably planarized so that the top surface of the conductive layer is level with the top surface of the first insulating layer. The spacer portions are removed to form spacer openings. LDD regions are formed in the substrate in the spacer opening. A dielectric layer is formed over the substrate filling the spacer openings. Source/drain (S/D) regions are formed in the substrate under the elevated source drain (S/D) regions.
The present invention's raised source drain proves many advantages over the prior art process. The invention's CMP to define the gate and raised source drain is more manufacturable and less costly than prior art processes.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5422289 (1995-06-01), Pierce
patent: 5491099 (1996-02-01), Hsu
patent: 5804846 (1998-09-01), Fuller
patent: 5897357 (1999-04-01), Wu et al.
patent: 5915183 (1999-06-01), Gambino et al.
patent: 6015727 (2000-01-01), Wanlass
patent: 6133098 (2000-10-01), Ogura et al.
patent: 6214670 (2001-04-01), Shih et al.
patent: 6163572 (1994-06-01), None
Chan Lap
Lee James Yong Meng
Leung Ying Keung
Pan Yang
Pradeep Yelehanka Ramachandramurthy
Bowers Charles
Chartered Semiconductor Manufacturing Inc.
Nguyen Thanh
Pike Rosemary L. S.
Saile George O.
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