Method of making low K fluorinated silicon oxide

Details Method of making low K fluorinated silicon oxide Method of making low K fluorinated silicon oxide

2000-07-20

2001-10-16

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C427S579000, C438S783000, C438S784000, C438S788000

Reexamination Certificate

active

06303519

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a fluorinated silicon oxide layer with a low dielectric constant during wafer processing. More particularly, the present invention relates to a deposition method for making a fluorinated silicon oxide layer having a dielectric constant that can be reduced to less than or equal to 3.
2. Description of the Prior Art
As feature sizes shrink and the integration of integrated circuits (IC) increases, resistance-capacitance (RC) time delays are becoming one of the most critical issues of IC industry. RC time delays are caused by adjacent metallic wiring lines in which each line is carrying an electric current, and it is a serious problem in multi-level metallization processes for manufacturing integrated circuits. Disadvantageously, RC time delays usually lead to reduced response, increased device power consumption and poor electrical performance of an IC. The response and performance become worse as the spacing between two adjacent metallic wiring lines decreases.
RC time delays are a product of the resistance R of the metallic wiring lines and the parasitic capacitance C formed between them. Minimal RC time delays are desirable. In essence, there are two approaches for deducing RC time delays: a) using conductive materials with a lower resistance as a wiring line or, b) reducing the parasitic capacitance.
Obviously, copper is a good choice for a conductor owing to its low resistance (1.67-cm) over Al—Cu(5%) alloy, which is the most commonly used conductor in current multilevel metallization processes. However, with the ever-increasing demand on performance, changing the metallic material appears to be inadequate to support future requirements. Consequently, some organic dielectric materials with low dielectric constants, such as polyimide (PI) and HSQ (hydrogen silsequioxane) etc., are rapidly coming into use to reduce parasitic capacitance. Unfortunately, most organic dielectric materials have metal adhesion issues and stability problems in a thermally active environment.
Since they are without the above-mentioned problems, low K inorganic materials are particularly desirable for intermetal dielectric (IMD) layers to reduce the RC time delay of an interconnect metallization circuit, to prevent cross talk between the different levels of metallization. Presently, many approaches for obtaining lower dielectric constants have been proposed. One of the more promising solutions is the incorporation of fluorine into a silicon oxide layer, also known as fluorinated silicon glass (FSG) films. A variety of different precursor gases and liquids have been employed as the source of fluorine in the formation of these FSG films. Some of these precursors include NF
3
, HF, SF
6
, CF
4
, C
2
F
6
, C
2
Cl
3
F
3
and triethoxyfluorosilane (TEFS).
Please refer to FIG.
1
A and FIG.
1
B. FIG.
1
A and
FIG. 1B
are diagrams illustrating, respectively, the dielectric constant (K) versus fluorine percentage in an FSG film, and the refraction index (RI) versus fluorine percentage. In
FIG. 1A
, the dielectric constant of an undoped silicon glass (USG) is about 3.9. Basically, as the concentration of the incorporated fluorine increases, the dielectric constants of FSG films decreases. However, the reported lowest stable dielectric constants can be achieved only down to about 3.5 to 3.2 according to the prior art method. As shown in
FIG. 1B
, as the fluorine percentage increases the RI decreases. The RI of an USG film is about 1.456.
It should be noted that none of the existing methods for preparing FSG films are capable of making a film having a stable dielectric constant that is less than 3.2. Additionally, some poorly formed FSG films may absorb moisture from the atmosphere, or from the reaction products associated with the deposition process. The absorption of water raises the dielectric constant of the FSG films.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of making a low K FSG film.
Another objective of the present invention is to provide a method of making an FSG film having a stable dielectric constant that is less than or equal to 3.2.
Still another objective of the present invention is to provide a method for depositing an FSG film that has reduced water and moisture absorptivities.
Still another objective of the present invention is to provide a CVD method for depositing an FSG film having a dielectric constant that is less than 3.2 by controlling the RI and O/F ratio.
The present invention provides a method of forming a fluorinated silicon oxide layer or an FSG film on a semiconductor wafer. In accordance with the present invention, the semiconductor wafer is first placed in a reacting chamber. The method includes introducing a fluorine-rich gas into the reacting chamber, introducing an oxygen-rich gas into the reacting chamber, creating a plasma environment in the reacting chamber to deposit fluorinated silicon oxide on the semiconductor wafer, and adjusting the flow rate of the oxygen-rich gas till the ratio of the flow rate of the oxygen-rich gas to the total flow rate of the fluorine-rich gas and silicon-rich gas is less than or equal to a pre-selected value to form the fluorinated silicon oxide layer. The refraction index (RI) of the fluorinated silicon oxide layer must be greater than or equal to 1.46. The initial flow rate of the oxygen-rich gas is greater than that of the fluorine-rich gas but less than twice the initial flow rate of the fluorine-rich gas. The plasma environment may be a high-density plasma.
In a preferred embodiment of the present invention, the fluorine-rich gas comprises SiF
4
and a silicon-rich gas. The silicon-rich gas is comprised of silane, or tetra-ethoxysilane (TEOS). The oxygen-rich gas is ultra-purified oxygen. Argon or helium are introduced into the reacting chamber as a carrier gas. By adjusting the flow rate of the oxygen gas to meet that the ratio of the flow rate of the oxygen gas to the total flow rate of the fluorine-rich gas, which is less than or equal to 2, the pre-selected value of oxygen to fluorine (O/F) ratio can be obtained. The plasma environment is created under the following conditions: (1) a top power of 700 to 5000 W; (2) a temperature of 300 to 500 j ;and (3) a pressure of 3 mtorr to 10 torr.


REFERENCES:
patent: 5563105 (1996-10-01), Dobuzinsky et al.
patent: 5660895 (1997-08-01), Lee et al.
patent: 6121162 (2000-09-01), Endo
Shannon et al., “Study of the material properties and suitability of plasma deposited fluorine-doped silicon dioxides for low dielectric constant interlevel dielectrics”, Thin Solid Films, 270 (1995) 498-502.*
Shapiro et al., “CVD of fluorosilicate glass for ULSI applications”, Thin Solid Films, 20 (1995) 503-507.*
Chang et al., “A manufacturable and reliable low-k inter-metal dielectric using fluorinated oxide (FSG)”, IEEE Inter. Conf. on Interconnect Tech, 1999, 131-133.*
Barth et al., “Integration of copper and fluorosilicate glass for 0.18 &mgr;m interconnections”, Proc. of the 2000 Inter. Interconnect Tech. Conf., 2000, 219-221.

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