Method for introducing an equivalent RC circuit in a MOS...

Details Method for introducing an equivalent RC circuit in a MOS... Method for introducing an equivalent RC circuit in a MOS...

2000-10-19

2001-10-16

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S210000, C438S217000

Reexamination Certificate

active

06303444

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to transistor devices and, more particularly, to low power and ultra-low power MOS devices.
BACKGROUND OF THE INVENTION
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power and ultra-low power transistor devices and systems. To meet this demand devices are emerging which have extremely low threshold voltages.
There are a number of factors that contribute to the magnitude of a device's threshold voltage. For example, to set a device's threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a device's threshold voltage by a few tens or even hundreds of millivolts. Further, dimensional variations, such as oxide thickness, channel width, channel length, charge trapping in materials and interfaces, and environmental factors, such as operating temperature fluctuations, can shift the threshold voltage.
Lowering the threshold voltage of a device typically decreases active power dissipation by permitting the same performance to be achieved at a lower supply voltage. However, lowering the threshold voltage of a device normally increases standby power dissipation by increasing device leakage and devices having low threshold voltages can leak so much current when their circuits are in a sleep or standby mode that the gains made by lowering the threshold voltage are outweighed by the power lost to leakage.
Consequently, it is particularly desirable in low-threshold devices to provide a mechanism for tuning the threshold voltage to account for these and other variations. Tuning the threshold voltage of a device can be accomplished using back biasing, i.e. controlling the potential between a device's well and source. See James B. Burr, “Stanford Ultra-Low Power CMOS,” Symposium Record, Hot Chips V, pp. 7.4.1-7.4.12, Stanford, Calif. 1993, which is incorporated, in its entirety, herein by reference. Back-biasing is used to electrically tune the transistor thresholds by reverse biasing the bulk of each MOS transistor, relative to the source, to adjust the threshold potentials. Typically, the potential will be controlled through isolated contacts to the source and well regions together with circuitry necessary for independently controlling the potential of these two regions.
FIG. 1A
illustrates a prior art device
100
A in which each of an NFET
101
and a PFET
102
essentially constitutes a four-terminal device. NFET
101
is made up of an N-region source
103
, a gate electrode
104
, an N-region drain
105
, and a P-bulk material
106
. Similarly, PFET
102
includes P-region source
108
, a gate electrode
109
and a P-region drain
110
formed in an N-well
111
. The device of
FIG. 1A
also includes a P plug that forms a well tie
112
for P-bulk material
106
, and an N plug that forms a well tie
113
for N-well
111
.
In the back-biased CMOS design of
FIG. 1A
, well tie
112
of bulk material
106
is electrically isolated from source
103
of NFET
101
by providing a separate metallic rail contact
116
which is spaced from metallic rail contact
114
of source
103
. Rail contact
116
is connected to a bias voltage source Vpw. Likewise, well contact
113
of N-well
111
is split off from source
108
of PFET
102
by providing a separate metallic rail contact
118
that is electrically isolated from metallic rail contact
115
of source
108
. Rail contact
118
is connected to a bias voltage source Vnw.
According to the structure of prior art device
100
A, the substrate bias potential of NFET
101
is set by Vpw, and that of PFET
102
is set by Vnw. In other designs, a number of transistors are formed in a common well. In these designs, the bias potential may be routed within a surface well.
FIG. 1B
illustrates a device
100
B similar to device
100
A of
FIG. 1A
, except that bulk material
106
of the NFET
101
in FIG.
1
B. is biased to Vpw by way of a metallic back plane
119
, rather than by way of well tie
116
as shown in FIG.
1
A.
FIG. 1C
shows a portion of prior art back biased device
100
A including NFET
101
. In the discussion below, NFET
101
was chosen for illustrative purposes only. Those of skill in the art will recognize that PFET
102
could also have been chosen and that the discussion and effects discussed below would be equally applicable, with the exception that the polarities would be reversed.
In
FIG. 1C
, the well-known effect of coupling capacitance between gate
104
and bulk material
106
is represented by gate-bulk coupling capacitance
150
and the well known effects of coupling capacitance between drain
105
and bulk material
106
is represented by drain-bulk coupling capacitance
152
. Due to gate-bulk coupling capacitance
150
, there is a tendency for the voltage of bulk material
106
, V-bulk, to track the voltage on gate
104
. As discussed in more detail below, if this tracking were allowed, there is a tendency to raise V-bulk and decrease the threshold voltage of NFET
101
as device
101
turns on, and, as discussed above, lowering the threshold voltage of a device such as NFET
101
has several benefits. However, in the prior art, a significant amount of effort, and virtually all teaching, was directed to keeping V-bulk constant during a switching event and preventing significant changes in the potential of bulk material
106
during a switching event. To this end, it was taught that bulk material
106
should be the lowest resistance possible and that bulk material
106
should be connected as directly as possible to ground or some other drain-off potential.
The main reason that the prior art taught keeping V-bulk constant, and bulk material
106
as low a resistive value as possible, is that in prior art CMOS designs two problems were always being dealt with: large impact ionization currents and/or latch up.
Impact ionization currents are created because the potentials in standard CMOS devices are high, on the order of 1.5 to 5.0 volts. At these potentials, charge carriers acquire so much kinetic energy that the impact of the carriers at the drain end of the channel can result in the generation of electron-hole pairs. Typically, in an NFET, the electrons move across the channel to the drain while the holes move into bulk material
106
thus creating potentially large sub-currents in bulk material
106
. In the prior art, if bulk material
106
were composed of even moderately resistive material, these sub-currents would result in large voltage drops throughout bulk material
106
.
FIG. 1D
shows a graph of the natural log of the substrate current in an N-well (Inw) and P-well (Ipw) due to impact ionization as a function of the source to drain potential (Vds) of a device. It is worth noting for later reference that at a Vds of 1.0 volts (
120
) or less, there is virtually no impact ionization current, while at the typical prior art CMOS Vds of 1.5 (
123
) to 5.0 (
125
) volts the impact ionization current is relatively high.
In addition to minimizing the effects of impact ionization current, the prior art taught that bulk material
106
must be low resistance, and kept at a constant potential, to avoid latch-up. Latch-up is a well-known result of CMOS design that inherently includes parasitic bipolar transistors cross-coupled in the device. As a result of these parasitic bipolar transistors, if the potential of bulk material (Vpw)
106
becomes sufficiently large and forward biased, or if the n-well potential (Vnw) of n-well
111
(see
FIG. 1A
) becomes sufficiently lower than the supply voltage (Vdd), a short is created between ground (gnd) and supply voltage (Vdd). This short could draw enough current to not only shut down or “latch-up” the device, but in many cases,

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