Method of fabricating a bottom electrode

Details Method of fabricating a bottom electrode Method of fabricating a bottom electrode

2000-10-10

2001-11-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S255000, C438S256000, C438S396000, C438S397000, C438S398000, C438S399000

Reexamination Certificate

active

06312985

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a bottom electrode.
2. Description of the Related Art
As the integration of the semiconductor devices increases and the linewidth thereof decreases, it becomes desirable to form more semiconductor devices in a limited area. Due to limitations imposed by the fabrication process, it is difficult to achieve a highly integrated circuit. In addition, because difficulties exist in forming a highly integrated device, it is hard to ensure the reliability of the device. Therefore, how to fabricate highly integrated semiconductor devices has became the main topic of the recent research on semiconductor fabrication at the 0.13 micron level.
FIG. 1
is a schematic, cross-sectional view illustrating a conventional method of forming a bit line and a bottom electrode.
A metal oxide semiconductor (MOS) is formed on the substrate
100
. The MOS includes a gate
102
on the substrate
100
, a spacer
104
on the sidewall of the gate
102
and the source/drain region
106
in the substrate
100
beside the gate
102
. A dielectric layer
108
is formed over the substrate
100
to cover the MOS. A bit line
110
is formed through the dielectric layer
108
to electrically couple with the source/drain region
106
. A dielectric layer
112
is formed over the substrate
100
to cover the bit line
110
. A bottom electrode
114
is formed through the dielectric layers
108
and
112
to electrically couple with the source/drain region
106
.
In the conventional method, devices, such as bit line
110
and the bottom electrode
114
are separated from each other. Consequently, the integration of the semiconductor circuit cannot be effectively increased. Thus, there is a need to further increase the integration of semiconductor devices.
In addition, due to the fabrication limitation for forming semiconductor devices in a limited area, box-shaped capacitors are usually formed. However, the conventional box-shaped capacitor cannot provide sufficient capacitance. Thus, the capacitance of the conventional capacitor is limited.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a bottom electrode. A first dielectric layer having a first opening is formed over a substrate. The first opening exposes a portion of a conductive layer in the substrate. A first liner layer is formed on a sidewall of the first opening. A conductive plug is formed in the opening. A plurality of bit lines is formed next to the first opening. A second liner layer is formed over the substrate to cover the bit lines, the first liner layer, and the conductive plug. A node contact opening is formed in the second liner layer to expose a portion of the conductive plug. A second dielectric layer is formed over the substrate. A second opening is formed in the second dielectric layer to expose the node contact opening and a portion of the second liner layer. A conformal conductive layer is formed in the opening.
In contrast with the conventional method, which has devices separated from each other, the devices of the present invention are next and closer to each other. Thus, the integration of the semiconductor devices fabricated by the present invention is effectively increased. In addition, since the first liner layer and the second liner layer are used to isolate the bit lines from the bottom electrode, the reliability of the devices is enhanced.
In addition, because of the liner layers provide isolation between the bottom electrode and the bit line, the opening for forming the bottom electrode overlaps with the bit line when viewed from the top. Thus, the opening for forming the bottom electrode can be wider than the conductive plug. The surface area of the bottom electrode is thus further increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5318925 (1994-06-01), Kim
patent: 5654236 (1997-08-01), Kasai
patent: 6020236 (2000-02-01), Lee et al.
patent: 6083831 (2000-07-01), Dennison
patent: 6130128 (2000-10-01), Lin
patent: 6165839 (2000-12-01), Lee et al.
patent: 6187625 (2001-02-01), Lin et al.
patent: 6232176 (2001-05-01), Parekh et al.

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