Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-09
2001-11-27
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S429000, C438S416000, C438S271000
Reexamination Certificate
active
06323090
ABSTRACT:
BACKGROUND OF THE INVENTION
Traditional power transistors are constructed on planar semiconductor wafers. Such conventional devices are described in the following four references. B. J. Baliga et al., “The Insulated Gate Rectifier (IGR): A New Power Switching Device”,
Proceeding of the IEDM,
1982, pp.264-267. B. J. Baliga, “How the Super-Transistor Works”,
Scientific American: “The Solid State Century”,
1997 pp. 34-41. U.S. Pat. No. 4,639,754, C. F. Wheatley et al., Jan. 27, 1987. U.S. Pat. No. 5,086,324, H. Hagimo, Feb. 4, 1992. However some transistor were developed in which the structure is nonplanar. The nonplanar devices are often called “V groove” devices, “V Mos”, “U Mos”, “trench etched Mosfets”, etc., describing in their name the shape of the surface after the etching process. Such devices are described in the following six references. T. D. Mok and C. A. T. Salama, “The Characteristics and Application of a V-Shaped Notched-Channel VFET,”
Solid State Electronics,
1976 Vol. 19 pp.159-166. B. Farzan and C. A. T. Salama, “Depletion V-Groove MOS (VMOS) Power Transistors”,
Solid State Electronics,
1976 Vol. 19 pp.297-306. C. A. T. Salama, “A New Short Channel MOSFET Structure (UMOST),
Solid State Electronics,
1977 Vol. 20, pp.1003-1009. Paul Ou-Yang, “Double Ion Implanted V-MOS Technology,”
IEEE Journal of Solid State Circuits,
Vol. Sc-12, No. 1, February 1977. A. A. Tamer et al., “Numerical Comparison of DMOS, VMOS, and UMOS Power Transactions”,
IEEE Transistors on Electron Devices,
Vol. Ed-30, No.1, January 1983. U.S. Pat. No. 4,199,774, “Monolithic Semiconductor Switching Device” J. D. Plummer, Apr. 22, 1980.
Some of the advantages cited for the non-planar structures include the following. a. For low voltage Mosfets, typically below about 200 v breakdown, reduced “on” resistance. b. Higher cell density, which results in higher gain devices. c.
FIG. 1
illustrates a conventional V groove Mosfet
2
in which the conducting channels
4
,
6
under gate
8
are angled towards substrate
10
, thus improving current spreading in the drift regions
12
,
14
,
16
in n− epi layer
18
, thus reducing the J FET effect. However, due to the more complex processing required in etching the grooves or trenches in the top surface of the FETs, and the poorer reliability of nonplanar devices, as will be explained below, these devices are not the preferred ones when it came to power Mosfets and Igbts. The standard planar DMOS devices are preferred in all voltage ranges, especially in the higher voltage ranges, about 100 v and above.
Power transistors are produced in two typical structures, one is epitaxial (epi) based and the other is bulk based. The first type is composed of a low resistivity semiconductor (SC) substrate on which a layer of higher resistivity SC material is grown epitaxially, like the example shown in
FIG. 1
, where epi layer
18
is grown on substrate
10
. The epi resistivity and thickness are selected for the desired breakdown voltage (BV) of the device. The bulk structure, on the other hand, is composed of one type of resistivity SC region, typically a high resistivity float zone (FZ) grown SC wafer. For clarity of illustration the examples discussed will be Si SC crystal material. The same concepts apply to other SC materials like GaAs, SiC, etc. In both structures, devices have been produced where the etching of the grooves was done on the surface of the high resistivity region, followed by the gate oxidations. The etching of the grooves creates damage, uneven surface morphology, particles, decoration or delineation of crystal defects, etc., which hampers the subsequent critical processing steps on the surface of these devices. The top surface of the SC device is the critical yield and performance critical surface. The focus of SC processing is to minimize surface defects in order to increase the yield. Yet the etching processes used to create the grooves on the top surfaces do the opposite—they reduce the yield. The sharp corners and internal edges of these grooves create weak points in the gate oxide, accumulate contaminants and particles during processing which are difficult to remove in subsequent cleaning processes, thus create weak and contaminated gate oxides, such as gate oxide region
20
in FIG.
1
. Thus, V groove, U groove, or trench Mosfets often have unstable turn on voltage, called threshold voltages (Vt) in their data sheets, have low oxide breakdown voltage, and have high failure rates under gate voltage bias tests.
Furthermore, as shown in
FIG. 1
, the fact that the groove is etched from the top surface into the high resistivity epi layer
18
, the n− epi layer in this example, reduces the net epi layer thickness under the tip
21
of the groove formed in epi layer
18
. This thickness is
22
is less than the original, as-deposited epi thickness
24
. The epi thickness
24
is usually selected to get the desired BV of the device. If the effective thickness is reduced by etching, it causes reduced BV, or it increases the electric field in the given device, which increases the stress on the gate oxide region
4
and accelerates its deterioration. To reduce the effect of this problem, conventional techniques often involve using a thicker epi layer to begin with. However, epi growth is an expensive process and renders the starting material more expensive when compared to bulk (i.e., non-epi based substrate), single crystal substrate or the material needed for planar transistors. Hence, this is a significant disadvantage of conventional nonplanar devices. Another conventional nonplanar solution has been to increase the thickness of gate oxide region
20
at tip
21
, to be able to sustain reliably the extra field strength in these pointed regions. Thicker gate oxide regions mean longer oxidation steps, reduced gain and on resistance, thus reduced cost/performance ratio when compared to the planar device. Because of this, these conventional nonplanar devices are considered more suitable for low voltage devices, where the electric fields are lower, typical with BV below about 70 v.
The grooves and trenches produced in epi layers of conventional nonplanar devices impose severe step coverage problems for any deposited layers on top of the surface, like gate electrode material: metal or poly Si, passivation or interlayer insulators like oxide, nitride, polymers, polyimide etc. Also, because conventional nonplanar devices are dependent on grooves etched from the top surface, one is limited to what is possible by only etching from the top.
SUMMARY OF THE INVENTION
This invention relates to semiconductor devices, such as planar and non-planar transistor structures, and methods for making the semiconductor devices that can provide performance advantages, better reliability, and higher manufacturing yields than conventional devices and methods.
A method according to the invention starts by creating a recess in the upper surface of a base layer of a semiconductor device. Next, an epitaxial (epi) layer is grown on the upper surface of the base layer. A semiconductor element, such as a well or a gate, is formed on the epi layer; the semiconductor element is typically aligned with the recess in the upper surface of the base layer. The growing step is preferably carried out in a manner to create a surface depression in the outer surface of the epi layer, the surface depression being generally aligned with the recess. The present invention is especially useful for making power transistors.
The invention takes advantage of the nonplanar structure at the outer surface of the epi layer while providing the option of smoothing out the outer surface of the epi layer if desired. Since the surface depression is created in the outer surface of the epi layer with the present invention, the outer surface of the epi layer, which is the critical surface, does not have the drawbacks normally associated with trenching, grooving or other steps normally associated with nonplanar devices, including creating weak points in the gate oxide, accumulating of
Elms Richard
Ixys Corporation
Smith Bradley
Townsend and Townsend / and Crew LLP
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